tree 25252b3dc8c636a3af2264a414c6085e3471bf7e
parent 05e740fc40e409dcf8d592f4bbeaf87dc92140c5
author Stefan Reinauer <stefan.reinauer@coreboot.org> 1335387503 +0200
committer Stefan Reinauer <stefan.reinauer@coreboot.org> 1335393995 +0200

Revamp Intel microcode update code

- add GPLv2 + copyright header after talking to Ron
- "bits" in struct microcode served no real purpose but
  getting its address taken. Hence drop it
- use asm volatile instead of __asm__ volatile
- drop superfluous wrmsr (that seems to be harmless but
  is still wrong) in read_microcode_rev
- use u32 instead of unsigned int where appropriate
- make code usable both in bootblock and in ramstage
- drop ROMCC style print_debug statements
- drop microcode update copy in Sandybridge bootblock

Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/928
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>