mb/google/brask/variants/moli: update overridetree
Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC.
BUG=b:220039297
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: If83031edcd90ea746704590765102b9b0dee03c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb
index eb13b06..2048b61 100644
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -4,6 +4,11 @@
option OPT_HDMI 1
option OPT_DP 2
end
+ field STORAGE 4 5
+ option STORAGE_UNKNOWN 0
+ option STORAGE_NVME 1
+ option STORAGE_EMMC 2
+ end
end
chip soc/intel/alderlake
# Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
@@ -12,10 +17,10 @@
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
- register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_Type-A Port A2
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_Type-A Port A3
- register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2_Type-A Port A9
- register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP3
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port2
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
+ register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP3
register "cnvi_bt_audio_offload" = "true"
device domain 0 on
device ref tcss_dma0 on
@@ -32,7 +37,9 @@
.clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
- end # SSD gen4
+ probe STORAGE STORAGE_NVME
+ probe STORAGE STORAGE_UNKNOWN
+ end # SSD
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
@@ -91,10 +98,10 @@
register "srcclk_pin" = "3"
device generic 0 on end
end
- end # PCIE8 SD card
- device ref pcie_rp9 off end #pcie_rp 9 Empty
- device ref pcie_rp10 off end #pcie_rp 10 Empty
- device ref pcie_rp11 off end #pcie_rp 11 Empty
+ end # SD card
+ device ref pcie_rp9 off end #pcie_rp 9 Empty
+ device ref pcie_rp10 off end #pcie_rp 10 Empty
+ device ref pcie_rp11 off end #pcie_rp 11 Empty
device ref pcie_rp12 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
@@ -102,14 +109,19 @@
register "srcclk_pin" = "1"
register "reset_delay_ms" = "50"
register "enable_delay_ms" = "20"
- device generic 0 alias emmc_rtd3 on end
+ device generic 0 alias emmc_rtd3 on
+ probe STORAGE STORAGE_EMMC
+ probe STORAGE STORAGE_UNKNOWN
+ end
end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
register "pch_pcie_rp[PCH_RP(12)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
- end # PCIE12 BH799BB
+ probe STORAGE STORAGE_EMMC
+ probe STORAGE STORAGE_UNKNOWN
+ end # BH799BB
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]