southbridge/intel/lynxpoint: Fix undefined behavior
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 3d01cd6..006bec2 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -193,6 +193,8 @@
rp = root_port_number(dev);
if (!dev->enabled) {
+ static const uint32_t high_bit = (1UL << 31);
+
/* Configure shared resource clock gating. */
if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
@@ -214,7 +216,7 @@
}
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
- pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));
+ pci_update_config32(dev, 0x420, ~high_bit, high_bit);
/* Per-Port CLKREQ# handling. */
if (is_lp && gpio_is_native(18 + rp - 1))