nb/intel/gm45: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: I18f40d1bc3172b3c1b6b4828cefdb91aea679ba2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51880
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 09df12d..a961481 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -14,21 +14,21 @@
int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff;
int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION);
- MCHBAR32(0x28) = IOMMU_BASE1 | 1; /* HDA @ 0:1b.0 */
+ mchbar_write32(0x28, IOMMU_BASE1 | 1); /* HDA @ 0:1b.0 */
if (stepping != STEPPING_B2) {
/* The official workaround is to run SMM every 64ms.
The only winning move is not to play. */
- MCHBAR32(0x18) = IOMMU_BASE2 | 1; /* IGD @ 0:2.0-1 */
+ mchbar_write32(0x18, IOMMU_BASE2 | 1); /* IGD @ 0:2.0-1 */
} else {
/* write-once, so lock it down */
- MCHBAR32(0x18) = 0; /* disable IOMMU for IGD @ 0:2.0-1 */
+ mchbar_write32(0x18, 0); /* disable IOMMU for IGD @ 0:2.0-1 */
}
if (me_active) {
- MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */
+ mchbar_write32(0x10, IOMMU_BASE3 | 1); /* ME @ 0:3.0-3 */
} else {
- MCHBAR32(0x10) = 0; /* disable IOMMU for ME */
+ mchbar_write32(0x10, 0); /* disable IOMMU for ME */
}
- MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */
+ mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */
/* clear GTT */
u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC);
@@ -48,7 +48,7 @@
}
if (stepping == STEPPING_B3) {
- MCHBAR8(0xffc) |= 1 << 4;
+ mchbar_setbits8(0xffc, 1 << 4);
const pci_devfn_t peg = PCI_DEV(0, 1, 0);
/* FIXME: proper test? */
@@ -57,5 +57,5 @@
}
/* final */
- MCHBAR8(0x94) |= 1 << 3;
+ mchbar_setbits8(0x94, 1 << 3);
}