tree 1e18007a6157df7d79948f01af62a2d8ec6e2992
parent a62cb5693b93a4bec3d4c0ae072d9622d6a5ea0f
author Tim Wawrzynczak <twawrzynczak@chromium.org> 1639023590 -0700
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1640198499 +0000

drivers/generic/bayhub_lv2: Work around known errata

The Bayhub LV2 has a known errata wherein PCI config registers at
offsets 0x234, 0x238, and 0x24C will only correctly accept writes
when they are addressed via a DWORD (32-bit) wide write operation
on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop
latency register, therefore add a finalize callback to this driver
which will program the LTR max-snoop/no-snoop register with a 32-bit
write using the values from pciexp_get_ltr_max_latencies().

BUG=b:204343849
TEST=verified the PCI config space writes took effect on google/taeko

Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>