2ms is enough time to accurately obtain the clock rate.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 27c89e3..1127867 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -18,8 +18,8 @@
  * device.
  */
 
-#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
-#define CALIBRATE_DIVISOR  (20*1000) /* 20ms / 20000 == 1usec */
+#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */
+#define CALIBRATE_DIVISOR  (2*1000) /* 2ms / 2000 == 1usec */
 
 static unsigned long long calibrate_tsc(void)
 {