soc/intel/apollolake: Bypass FSP's deassertion of PERST# signal.

BUG=b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I1858c7843d16b6b63fc30762a889916bbb9b781a
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 1db2982..a8a0dd1 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -304,6 +304,17 @@
 		die("Can not find SoC devicetree\n");
 
 	m_cfg->PrmrrSize = config->PrmrrSize;
+
+	/* FSP performs a PERST# signal deassertion for PCIe ports with
+	 * the GPIO address specified in these UPDs. Over-ride the default
+	 * addresses with 0 to bypass PERST# signal deassertion in FSP.
+	 */
+	m_cfg->RootPort0Perst = 0;
+	m_cfg->RootPort1Perst = 0;
+	m_cfg->RootPort2Perst = 0;
+	m_cfg->RootPort3Perst = 0;
+	m_cfg->RootPort4Perst = 0;
+	m_cfg->RootPort5Perst = 0;
 #endif
 }