commit 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d
author Elyes HAOUAS <ehaouas@noos.fr> Thu Aug 09 18:55:58 2018 +0200
committer Martin Roth <martinroth@google.com> Fri Aug 10 21:25:53 2018 +0000
tree 7b5096ca1f81fecf70418020aba184e446f995e0
parent 1895838e7a3807a6fce324f0dfed193a3821f6df

src: Fix typo

Change-Id: I689c5663ef59861f79b68220abd146144f7618de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/cannonlake/reset.c

diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c
index 26f0a63..140fbff 100644
--- a/src/soc/intel/cannonlake/reset.c
+++ b/src/soc/intel/cannonlake/reset.c
@@ -74,7 +74,7 @@
 		printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n");
 		return -1;
 	}
-	printk(BIOS_DEBUG, "Heci recieve success!\n");
+	printk(BIOS_DEBUG, "Heci receive success!\n");
 	return 0;
 }
 

src/soc/intel/common/block/cse/cse.c

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 8651297..4b53117 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -443,7 +443,7 @@
 		do {
 			received = recv_one_message(&hdr, p, left);
 			if (!received) {
-				printk(BIOS_ERR, "HECI: Failed to recieve!\n");
+				printk(BIOS_ERR, "HECI: Failed to receive!\n");
 				return 0;
 			}
 			left -= received;

src/soc/intel/skylake/bootblock/pch.c

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 4c88ed5..26ea56a 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -124,7 +124,7 @@
 	pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
 
 	/* Program TCO Base */
-	pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);
+	pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS);
 
 	/* Enable TCO in SMBUS */
 	pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);
@@ -133,7 +133,7 @@
 	 * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
 	 * to [SMBUS PCI offset 50h[15:5], 1].
 	 */
-	pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));
+	pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1));
 
 	/* Program TCO timer halt */
 	tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);

src/soc/intel/skylake/include/soc/iomap.h

diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index f2fde71..475d79d 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -87,7 +87,7 @@
 #define ACPI_BASE_ADDRESS	0x1800
 #define ACPI_BASE_SIZE		0x100
 
-#define TCO_BASE_ADDDRESS	0x400
+#define TCO_BASE_ADDRESS	0x400
 #define TCO_BASE_SIZE		0x20
 
 #define P2SB_BAR		CONFIG_PCR_BASE_ADDRESS