commit | 3d3728b0d04201fd97b56b2249883ed1bcebf457 | [log] [tgz] |
---|---|---|
author | Angel Pons <th3fanbus@gmail.com> | Tue Feb 23 14:08:38 2021 +0100 |
committer | Patrick Georgi <pgeorgi@google.com> | Mon Mar 01 08:23:37 2021 +0000 |
tree | e24c1735b67869ee399f92ed96680b8d9b0e697d | |
parent | da43737c4ee04c282bbb31a42f21a094060dcc07 [diff] |
sb/intel/lynxpoint/me_9.x.c: Rename to me.c This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index d0b342b..a8de2fb 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -13,7 +13,7 @@ ramstage-y += sata.c ramstage-y += usb_ehci.c ramstage-y += usb_xhci.c -ramstage-y += me_9.x.c +ramstage-y += me.c ramstage-y += smbus.c ramstage-y += hda_verb.c ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c @@ -30,7 +30,7 @@ ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-y += smihandler.c me_9.x.c pch.c +smm-y += smihandler.c me.c pch.c smm-y += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me.c similarity index 100% rename from src/southbridge/intel/lynxpoint/me_9.x.c rename to src/southbridge/intel/lynxpoint/me.c