diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 67b0954..b2116f2 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -1,5 +1,6 @@
 ramstage-y += haswell_init.c
 subdirs-y += ../../x86/name
+romstage-y += romstage.c
 
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index f5ee82e..72b4958 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -24,7 +24,11 @@
 #include <cpu/x86/post_code.h>
 #include <cbmem.h>
 
-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
+ * and the space used by the reference code. These 2 values combined should
+ * be a power of 2 because the MTRR setup assumes that. */
+#define CACHE_AS_RAM_SIZE \
+	(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
 /* Cache 4GB - MRC_SIZE_KB for MRC */
@@ -166,9 +170,8 @@
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 
-	/* Set up the stack pointer below MRC variable space. */
-	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
-		  CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
+	/* Setup the stack. */
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
 	movl	%eax, %esp
 
 	/* Restore the BIST result. */
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index cb85078..8d91dba 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -101,6 +101,11 @@
 #define PSS_LATENCY_BUSMASTER		10
 
 #ifndef __ROMCC__
+
+#if defined(__PRE_RAM__)
+void romstage_main(unsigned long bist);
+#endif
+
 #ifdef __SMM__
 /* Lock MSRs */
 void intel_cpu_haswell_finalize_smm(void);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
new file mode 100644
index 0000000..f954b91
--- /dev/null
+++ b/src/cpu/intel/haswell/romstage.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <cbmem.h>
+#include <console/console.h>
+
+/* Mainboard needs to supply this symbol. */
+extern void romstage_main(unsigned long bist);
+
+void main(unsigned long bist)
+{
+	int i;
+	const int num_guards = 4;
+	const u32 stack_guard = 0xdeadbeef;
+	u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
+	                           CONFIG_DCACHE_RAM_SIZE -
+	                           CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+
+	printk(BIOS_DEBUG, "Setting up stack guards.\n");
+	for (i = 0; i < num_guards; i++)
+		stack_base[i] = stack_guard;
+
+	romstage_main(bist);
+
+	/* Check the stack. */
+	for (i = 0; i < num_guards; i++) {
+		if (stack_base[i] == stack_guard)
+			continue;
+		printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
+	}
+
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+}