src/nb: Use 'print("%s...", __func__)'
Change-Id: I7dd6dd8e8debe1b6419625fca38670be375ef581
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 98e30e7..05855f3f 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -88,9 +88,9 @@
/* verify */
if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {
- printk(BIOS_DEBUG, "gtt_setup is enabled.\n");
+ printk(BIOS_DEBUG, "%s is enabled.\n", __func__);
} else {
- printk(BIOS_DEBUG, "gtt_setup failed!!!\n");
+ printk(BIOS_DEBUG, "%s failed!!!\n", __func__);
return 1;
}
write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index f0ea142..cb3b943 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -111,7 +111,7 @@
case 2: return 533;
case 3: return 667;
default:
- printk(BIOS_DEBUG, "memclk: unknown register value %x\n",
+ printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__,
((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
}
return -1;
@@ -125,7 +125,7 @@
case 1: return 533;
case 3: return 667;
default:
- printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n",
+ printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__,
MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
@@ -135,7 +135,7 @@
case 1: return 533;
case 2: return 800;
default:
- printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n",
+ printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__,
MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 5a90807..2768a61 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -64,7 +64,7 @@
{
u32 reg32;
- printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
+ printk(BIOS_SPEW, " %s() medium=0x%x, coarse=0x%x\n", __func__, medium, coarse);
reg32 = MCHBAR32(C0DRT1 + channel_offset);
reg32 &= 0xf0ffffff;
@@ -73,7 +73,7 @@
/* This should never happen: */
if (coarse > 0x0f)
- printk(BIOS_DEBUG, "set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
+ printk(BIOS_DEBUG, "%s: coarse overflow: 0x%02x.\n", __func__, coarse);
/* medium control
*
@@ -99,7 +99,7 @@
static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine)
{
- printk(BIOS_SPEW, " normalize()\n");
+ printk(BIOS_SPEW, " %s()\n", __func__);
if (*fine < 0x80)
return 0;
@@ -126,7 +126,7 @@
/* find start of the data phase */
u32 reg32;
- printk(BIOS_SPEW, " find_preamble()\n");
+ printk(BIOS_SPEW, " %s()\n", __func__);
do {
if (*mediumcoarse < 4) {
@@ -156,7 +156,7 @@
static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine)
{
- printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
+ printk(BIOS_SPEW, " %s() mediumcoarse=%02x fine=%02x\n", __func__,
*mediumcoarse, *fine);
if (*fine >= 0x80) {
*fine -= 0x80;
@@ -183,7 +183,7 @@
{
u32 rcvenmt;
- printk(BIOS_SPEW, " find_strobes_low()\n");
+ printk(BIOS_SPEW, " %s()\n", __func__);
for (;;) {
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
@@ -219,7 +219,7 @@
int counter;
u32 rcvenmt;
- printk(BIOS_SPEW, " find_strobes_edge()\n");
+ printk(BIOS_SPEW, " %s()\n", __func__);
counter = 8;
set_receive_enable(channel_offset, *mediumcoarse & 3,
@@ -283,8 +283,7 @@
u8 mediumcoarse;
u8 fine;
- printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n",
- channel_offset ? 1 : 0);
+ printk(BIOS_SPEW, "%s() for channel %d\n", __func__, channel_offset ? 1 : 0);
/* Set initial values */
mediumcoarse = (sysinfo->cas << 2) | 3;