soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the
Broadwell SoC directory for now, to ease moving files around. The boards
were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 0d41d42..c98201e 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -13,7 +13,7 @@
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
#include <soc/cpu.h>
#include <delay.h>
@@ -121,7 +121,7 @@
root_port_config_update_gbe_port();
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
rpc.coalesce = config->pcie_port_coalesce;
}
@@ -436,7 +436,7 @@
static void pch_pcie_early(struct device *dev)
{
- config_t *config = config_of(dev);
+ const struct soc_intel_broadwell_pch_config *config = config_of(dev);
int do_aspm = 0;
int rp = root_port_number(dev);