soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne
The Cezanne SoC code was initially started as a copy of example/min86
which only provides enough code to make the SoC code build. Then the
different parts of the real SoC support was brought in patch by patch
which also helped cleaning up and untangling the code. Since the Cezanne
SoC code is now in a rather good shape and the Sabrina SoC is similar to
the Cezanne SoC from the coreboot side, the new SoC support is started
with a copy of the Cezanne code and all the needed changes will be
applied on top of that. In order for the build not to fail due to
duplicate files, this patch does not only copy the directory, but also
replaces most instances of the Cezanne name with Sabrina. Since the
needed blobs aren't available in the 3rdparty/amd_blobs repository yet,
the Cezanne blobs are used for now so that the build will succeed. As
soon as the proper blobs will be available in that repository, the code
will be switched over to use them.
As suggested by Nico, I added a "TODO: Check if this is still correct"
comment to the beginning of every copied file and all SOC_AMD_COMMON_*
Kconfig option selects which will be removed after re-verifying that
each file and each selected common code block is still correct for the
new SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
diff --git a/src/soc/amd/sabrina/chipset.cb b/src/soc/amd/sabrina/chipset.cb
new file mode 100644
index 0000000..486f42f
--- /dev/null
+++ b/src/soc/amd/sabrina/chipset.cb
@@ -0,0 +1,114 @@
+# TODO: Check if this is still correct
+
+chip soc/amd/sabrina
+ device cpu_cluster 0 on
+ end
+ device domain 0 on
+ device pci 00.0 alias gnb on end
+ device pci 00.2 alias iommu off end
+
+ device pci 01.0 on end # Dummy Host Bridge, do not disable
+ device pci 01.1 alias gpp_gfx_bridge_0 off end
+ device pci 01.2 alias gpp_gfx_bridge_1 off end
+ device pci 01.3 alias gpp_gfx_bridge_2 off end
+
+ device pci 02.0 on end # Dummy Host Bridge, do not disable
+ device pci 02.1 alias gpp_bridge_0 off end
+ device pci 02.2 alias gpp_bridge_1 off end
+ device pci 02.3 alias gpp_bridge_2 off end
+ device pci 02.4 alias gpp_bridge_3 off end
+ device pci 02.5 alias gpp_bridge_4 off end
+ device pci 02.6 alias gpp_bridge_5 off end
+ device pci 02.7 alias gpp_bridge_6 off end
+
+ device pci 08.0 on end # Dummy Host Bridge, do not disable
+ device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
+ device pci 0.0 alias gfx off end # Internal GPU (GFX)
+ device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
+ device pci 0.2 alias crypto off end # Crypto Coprocessor
+ device pci 0.3 alias xhci_0 off
+ chip drivers/usb/acpi
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 alias xhci_0_root_hub off
+ chip drivers/usb/acpi
+ device usb 3.0 alias usb3_port0 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.1 alias usb3_port1 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.0 alias usb2_port0 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.1 alias usb2_port1 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.2 alias usb2_port2 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.3 alias usb2_port3 off end
+ end
+ end
+ end
+ end
+ device pci 0.4 alias xhci_1 off
+ chip drivers/usb/acpi
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 alias xhci_1_root_hub off
+ chip drivers/usb/acpi
+ device usb 3.0 alias usb3_port4 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.1 alias usb3_port5 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.0 alias usb2_port4 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.1 alias usb2_port5 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.2 alias usb2_port6 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.3 alias usb2_port7 off end
+ end
+ end
+ end
+ end
+ device pci 0.5 alias acp off end # Audio Processor (ACP)
+ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
+ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
+ end
+ device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+ device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
+ device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
+ device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
+ device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
+ end
+ device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+ device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function
+ device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio
+ end
+
+ device pci 14.0 alias smbus on end # primary FCH function
+ device pci 14.3 alias lpc_bridge on end
+
+ device pci 18.0 alias data_fabric_0 on end
+ device pci 18.1 alias data_fabric_1 on end
+ device pci 18.2 alias data_fabric_2 on end
+ device pci 18.3 alias data_fabric_3 on end
+ device pci 18.4 alias data_fabric_4 on end
+ device pci 18.5 alias data_fabric_5 on end
+ device pci 18.6 alias data_fabric_6 on end
+ device pci 18.7 alias data_fabric_7 on end
+ end
+
+ device mmio 0xfedc2000 alias i2c_0 off end
+ device mmio 0xfedc3000 alias i2c_1 off end
+ device mmio 0xfedc4000 alias i2c_2 off end
+ device mmio 0xfedc5000 alias i2c_3 off end
+ device mmio 0xfedc9000 alias uart_0 off end
+ device mmio 0xfedca000 alias uart_1 off end
+ device mmio 0xfedd5000 alias emmc off end
+end