diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c
index 92c0e6c..8a067f2 100644
--- a/src/mainboard/asus/p2b-d/romstage.c
+++ b/src/mainboard/asus/p2b-d/romstage.c
@@ -28,7 +28,6 @@
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
index dd9e5d2..a47a298 100644
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ b/src/mainboard/asus/p2b-ls/romstage.c
@@ -28,7 +28,6 @@
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index 45d7c5e..54018f3 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -28,7 +28,6 @@
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index c049d9e..f42bef2 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -1044,9 +1044,9 @@
 		sz = spd_get_dimm_size(dimm_socket_address);
 
 		RAM_DEBUG_MESSAGE("dimm size =");
-		RAM_DEBUG_HEX32(sz.side1);
+		RAM_DEBUG_HEX32((u32)sz.side1);
 		RAM_DEBUG_MESSAGE(" ");
-		RAM_DEBUG_HEX32(sz.side2);
+		RAM_DEBUG_HEX32((u32)sz.side2);
 		RAM_DEBUG_MESSAGE("\n");
 
 		if (sz.side1 == 0)
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index 81b9fd8..ef2f45c 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -1,10 +1,14 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <spd.h>
 #include "raminit.h"
 #include <spd.h>
 #include <console/console.h>
 
+#if CONFIG_DEBUG_RAM_SETUP
 void dump_spd_registers(void)
 {
-#if CONFIG_DEBUG_RAM_SETUP
 	int i;
 	printk(BIOS_DEBUG, "\n");
 	for(i = 0; i < DIMM_SOCKETS; i++) {
@@ -30,5 +34,36 @@
 			printk(BIOS_DEBUG, "\n");
 		}
 	}
-#endif
 }
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\n");
+
+	for (i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\n");
+		}
+	}
+}
+#endif
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index b7d5b29..5fb613c 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -38,11 +38,10 @@
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
-#include "lib/debug.c"
 #define PRINT_DEBUG(x...)	printk(BIOS_DEBUG, x)
-#define PRINT_DEBUG_HEX8(x)	PRINT_DEBUG("%02x", x)
-#define PRINT_DEBUG_HEX16(x)	PRINT_DEBUG("%04x", x)
-#define PRINT_DEBUG_HEX32(x)	PRINT_DEBUG("%08x", x)
+#define PRINT_DEBUG_HEX8(x)	printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_HEX16(x)	printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_HEX32(x)	printk(BIOS_DEBUG, "%08x", x)
 #define DUMPNORTH()		dump_pci_device(NB)
 #else
 #define PRINT_DEBUG(x...)
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 4bc0796..de9b5ab 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -29,6 +29,8 @@
 void sdram_set_registers(void);
 void sdram_set_spd_registers(void);
 void sdram_enable(void);
-void dump_spd_registers(void);
 
+/* Debug */
+void dump_spd_registers(void);
+void dump_pci_device(unsigned dev);
 #endif				/* RAMINIT_H */
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 16a9089..88adc24 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -1,8 +1,13 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <spd.h>
+#include "i82810.h"
 #include "raminit.h"
 
+#if CONFIG_DEBUG_RAM_SETUP
 void dump_spd_registers(void)
 {
-#if CONFIG_DEBUG_RAM_SETUP
 	int i;
 	print_debug("\n");
 	for(i = 0; i < DIMM_SOCKETS; i++) {
@@ -34,5 +39,36 @@
 			print_debug("\n");
 		}
 	}
-#endif
 }
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\n");
+
+	for (i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\n");
+		}
+	}
+}
+#endif
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index df2916e..39507eb 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -35,17 +35,12 @@
 -----------------------------------------------------------------------------*/
 
 /* Debugging macros. */
-#define HAVE_ENOUGH_REGISTERS   0 /* Don't have enough registers to compile all
-				   * debugging code with ROMCC
-				   */
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG(x)		print_debug(x)
-#define PRINT_DEBUG_HEX8(x)	print_debug_hex8(x)
-#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
-#define PRINT_DEBUG_HEX32(x)	print_debug_hex32(x)
-// no dump_pci_device in src/northbridge/intel/i82810/
-// #define DUMPNORTH()		dump_pci_device(PCI_DEV(0, 0, 0))
-#define DUMPNORTH()
+#define PRINT_DEBUG(x...)	printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_HEX8(x)	printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_HEX16(x)	printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_HEX32(x)	printk(BIOS_DEBUG, "%08x", x)
+#define DUMPNORTH()		dump_pci_device(PCI_DEV(0, 0, 0))
 #else
 #define PRINT_DEBUG(x)
 #define PRINT_DEBUG_HEX8(x)
@@ -209,27 +204,14 @@
 		dimm_size = translate_i82810_to_mb[drp];
 		if (dimm_size) {
 			addr = (dimm_start * 1024 * 1024) + addr_offset;
-#if HAVE_ENOUGH_REGISTERS
-			PRINT_DEBUG("    Sending RAM command 0x");
-			PRINT_DEBUG_HEX8(reg8);
-			PRINT_DEBUG(" to 0x");
-			PRINT_DEBUG_HEX32(addr);
-			PRINT_DEBUG("\n");
-#endif
-
+			PRINT_DEBUG("    Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
 			read32(addr);
 		}
 
 		dimm_bank = translate_i82810_to_bank[drp];
 		if (dimm_bank) {
 			addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
-#if HAVE_ENOUGH_REGISTERS
-			PRINT_DEBUG("    Sending RAM command 0x");
-			PRINT_DEBUG_HEX8(reg8);
-			PRINT_DEBUG(" to 0x");
-			PRINT_DEBUG_HEX32(addr);
-			PRINT_DEBUG("\n");
-#endif
+			PRINT_DEBUG("    Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
 			read32(addr);
 		}
 
@@ -256,16 +238,11 @@
 	for (i = 0; i < DIMM_SOCKETS; i++) {
 		/* First check if a DIMM is actually present. */
 		if (smbus_read_byte(DIMM0 + i, 2) == 4) {
-			print_debug("Found DIMM in slot ");
-			print_debug_hex8(i);
-			print_debug("\n");
+			printk(BIOS_DEBUG, "Found DIMM in slot %d\n", i);
 
 			dimm_size = smbus_read_byte(DIMM0 + i, 31);
 
-			/* WISHLIST: would be nice to display it as decimal? */
-			print_debug("DIMM is 0x");
-			print_debug_hex8(dimm_size * 4);
-			print_debug("MB\n");
+			printk(BIOS_DEBUG, "DIMM is %dMB\n", dimm_size * 4);
 
 			/* The i810 can't handle DIMMs larger than 128MB per
 			 * side. This will fail if the DIMM uses a
@@ -274,10 +251,10 @@
 			 * Note: the factory BIOS just dies if it spots this :D
 			 */
 			if (dimm_size > 32) {
-				print_err("DIMM row sizes larger than 128MB not"
+				printk(BIOS_ERR, "DIMM row sizes larger than 128MB not"
 					  "supported on i810\n");
-				print_err
-				    ("Attempting to treat as 128MB DIMM\n");
+				printk
+				    (BIOS_ERR, "Attempting to treat as 128MB DIMM\n");
 				dimm_size = 32;
 			}
 
@@ -287,21 +264,17 @@
 			 */
 			dimm_size = translate_spd_to_i82810[dimm_size];
 
-			print_debug("After translation, dimm_size is 0x");
-			print_debug_hex8(dimm_size);
-			print_debug("\n");
+			printk(BIOS_DEBUG, "After translation, dimm_size is %d\n", dimm_size);
 
 			/* If the DIMM is dual-sided, the DRP value is +2 */
 			/* TODO: Figure out asymetrical configurations. */
 			if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) ==
 			    0xff) {
-				print_debug("DIMM is dual-sided\n");
+				printk(BIOS_DEBUG, "DIMM is dual-sided\n");
 				dimm_size += 2;
 			}
 		} else {
-			print_debug("No DIMM found in slot ");
-			print_debug_hex8(i);
-			print_debug("\n");
+			printk(BIOS_DEBUG, "No DIMM found in slot %d\n", i);
 
 			/* If there's no DIMM in the slot, set value to 0. */
 			dimm_size = 0x00;
@@ -311,9 +284,7 @@
 		drp |= dimm_size << (i * 4);
 	}
 
-	print_debug("DRP calculated to 0x");
-	print_debug_hex8(drp);
-	print_debug("\n");
+	printk(BIOS_DEBUG, "DRP calculated to 0x%02x\n", drp);
 
 	pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
 }
@@ -414,9 +385,7 @@
 	if (!d0.size && d1.size)
 		buff_sc |= 1 << 15;
 
-	print_debug("BUFF_SC calculated to 0x");
-	print_debug_hex16(buff_sc);
-	print_debug("\n");
+	printk(BIOS_DEBUG, "BUFF_SC calculated to 0x%04x\n", buff_sc);
 
 	pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
 }
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index 186589a..5279eff 100644
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -28,6 +28,8 @@
 void sdram_set_registers(void);
 void sdram_set_spd_registers(void);
 void sdram_enable(void);
-void dump_spd_registers(void);
 
+/* Debug */
+void dump_spd_registers(void);
+void dump_pci_device(unsigned dev);
 #endif
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 6915d78..1c93435 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -88,7 +88,7 @@
 }
 
 #if CONFIG_DEBUG_RAM_SETUP
-static void sdram_dump_mchbar_registers(void)
+void sdram_dump_mchbar_registers(void)
 {
 	int i;
 	printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index e3b8491..ede194c 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -71,4 +71,8 @@
 unsigned long get_top_of_ram(void);
 int fixup_i945_errata(void);
 void udelay(u32 us);
+
+#if CONFIG_DEBUG_RAM_SETUP
+void sdram_dump_mchbar_registers(void);
+#endif
 #endif				/* RAMINIT_H */
diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c
index 7688ab3..70b4800 100644
--- a/src/northbridge/via/vx800/dram_util.c
+++ b/src/northbridge/via/vx800/dram_util.c
@@ -193,7 +193,7 @@
 	PRINT_DEBUG_MEM
 	    ("---------------------------------------------------\r");
 	for (i = 0; i < 0x10; i++) {
-		PRINT_DEBUG_MEM_HEX32(i);
+		PRINT_DEBUG_MEM_HEX32((u32)i);
 		for (j = 0; j < 0x10; j++) {
 			ByteVal =
 			    pci_read_config8(PCI_DEV(0, DevNum, FuncNum),