diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index f8b4f18..10c0b89 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -27,6 +27,7 @@
 #include <romstage_handoff.h>
 
 #include <baytrail/iomap.h>
+#include <baytrail/irq.h>
 #include <baytrail/lpc.h>
 #include <baytrail/nvs.h>
 #include <baytrail/pci_devs.h>
@@ -116,6 +117,23 @@
 	sc_add_io_resources(dev);
 }
 
+static void sc_init(device_t dev)
+{
+	int i;
+	const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
+	const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
+	const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
+
+	/* Set up the PIRQ PIC routing based on static config. */
+	for (i = 0; i < NUM_PIRQS; i++) {
+		write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+	}
+	/* Set up the per device PIRQ routing base on static config. */
+	for (i = 0; i < NUM_IR_DEVS; i++) {
+		write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+	}
+}
+
 /*
  * Common code for the south cluster devices.
  */
@@ -412,7 +430,7 @@
 	.read_resources		= sc_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= NULL,
-	.init			= NULL,
+	.init			= sc_init,
 	.enable			= southcluster_enable_dev,
 	.scan_bus		= scan_static_bus,
 	.ops_pci		= &soc_pci_ops,