device: Add support for multiple PCI segment groups
Add initial support for multiple PCI segment groups. Instead of
modifying secondary in the bus struct introduce a new segment_group
struct element and keep existing common code.
Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment the
segment has to be set when creating the PCI domain.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index dae2401..a4409fb 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -296,7 +296,7 @@
ivhd_11->capability_offset = 0x40;
ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low;
ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high;
- ivhd_11->pci_segment_group = 0x0000;
+ ivhd_11->pci_segment_group = nb_dev->bus->segment_group;
ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info;
ivhd_11->iommu_attributes.perf_counters =
(IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf;
@@ -364,7 +364,7 @@
ivrs->ivhd.capability_offset = 0x40;
ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low;
ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high;
- ivrs->ivhd.pci_segment_group = 0x0000;
+ ivrs->ivhd.pci_segment_group = nb_dev->bus->segment_group;
ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info;
ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info;
/* Enable EFR if supported */