Convert AOpen DXPL Plus mainboard to CAR
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
requires cache-as-ram init code with AP SIPI protocol.
Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.
Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl
index 31cfa88..095df06 100644
--- a/src/mainboard/aopen/dxplplusu/dsdt.asl
+++ b/src/mainboard/aopen/dxplplusu/dsdt.asl
@@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/ioapic.h>
+
DefinitionBlock(
"dsdt.aml",
"DSDT",