Convert AOpen DXPL Plus mainboard to CAR
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
requires cache-as-ram init code with AP SIPI protocol.
Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.
Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
index bb8c321..a1a23f2 100644
--- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
+++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
@@ -96,7 +96,7 @@
Name (MSBF, ResourceTemplate ()
{
/* IOAPIC 0 */
- Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,)
+ Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,)
IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO)
IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO)