mb/google/fatcat: Add minimal code support for fatcat
This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
new file mode 100644
index 0000000..2c6ddd2
--- /dev/null
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -0,0 +1,108 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_GOOGLE_FATCAT_COMMON
+ def_bool n
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_SPI_ACPI
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_BOARDID
+ select EC_GOOGLE_CHROMEEC_ESPI
+ select EC_GOOGLE_CHROMEEC_SKUID
+ select GOOGLE_SMBIOS_MAINBOARD_VERSION
+ select HAVE_ACPI_TABLES
+ select I2C_TPM
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_DISABLE_STAGE_CACHE
+ select MAINBOARD_HAS_TPM2
+ select MB_COMPRESS_RAMSTAGE_LZ4
+ select PMC_IPC_ACPI_INTERFACE
+ select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
+ select SOC_INTEL_CSE_LITE_SKU
+ select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
+ select SOC_INTEL_CSE_SEND_EOP_ASYNC
+
+config BOARD_GOOGLE_BASEBOARD_FATCAT
+ def_bool n
+ select BOARD_GOOGLE_FATCAT_COMMON
+ select HAVE_SLP_S0_GATE
+ select MAINBOARD_HAS_CHROMEOS
+ select SOC_INTEL_IOE_DIE_SUPPORT
+ select SOC_INTEL_METEORLAKE_U_H
+ select SYSTEM_TYPE_LAPTOP
+ select TPM_GOOGLE_TI50
+
+config BOARD_GOOGLE_MODEL_FATCAT
+ def_bool n
+ select BOARD_GOOGLE_BASEBOARD_FATCAT
+
+config BOARD_GOOGLE_FATCAT
+ select BOARD_GOOGLE_MODEL_FATCAT
+ select HAVE_X86_64_SUPPORT
+ select USE_X86_64_SUPPORT
+
+if BOARD_GOOGLE_FATCAT_COMMON
+
+config BASEBOARD_DIR
+ string
+ default "fatcat"
+
+config CHROMEOS
+ select EC_GOOGLE_CHROMEEC_SWITCHES
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_MANUAL_RECOVERY
+ select HAS_RECOVERY_MRC_CACHE
+
+config DEVICETREE
+ default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+ default 512
+
+# FIXME: update below code as per board schematics
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x0
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x0
+
+config FMDFILE
+ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
+ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
+
+config HAVE_SLP_S0_GATE
+ def_bool n
+
+config MAINBOARD_DIR
+ default "google/fatcat"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Fatcat"
+
+config MAINBOARD_PART_NUMBER
+ default "Fatcat" if BOARD_GOOGLE_FATCAT
+
+# FIXME: update as per board schematics
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 0
+
+# FIXME: update as per board schematics
+config UART_FOR_CONSOLE
+ int
+ default 0
+
+config USE_PM_ACPI_TIMER
+ default n
+
+config VARIANT_DIR
+ string
+ default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT
+
+config VBOOT
+ select VBOOT_LID_SWITCH
+
+endif # BOARD_GOOGLE_FATCAT_COMMON
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
new file mode 100644
index 0000000..ccf1f6d
--- /dev/null
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+comment "Fatcat"
+
+config BOARD_GOOGLE_FATCAT
+ bool "-> Fatcat"
diff --git a/src/mainboard/google/fatcat/Makefile.mk b/src/mainboard/google/fatcat/Makefile.mk
new file mode 100644
index 0000000..11098e2
--- /dev/null
+++ b/src/mainboard/google/fatcat/Makefile.mk
@@ -0,0 +1,23 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
+
+subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
+subdirs-y += variants/$(VARIANT_DIR)
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/fatcat/board_info.txt b/src/mainboard/google/fatcat/board_info.txt
new file mode 100644
index 0000000..3d09984
--- /dev/null
+++ b/src/mainboard/google/fatcat/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Fatcat
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/fatcat/bootblock.c b/src/mainboard/google/fatcat/bootblock.c
new file mode 100644
index 0000000..6ee655e
--- /dev/null
+++ b/src/mainboard/google/fatcat/bootblock.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_early_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
new file mode 100644
index 0000000..5b20f00
--- /dev/null
+++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
@@ -0,0 +1,49 @@
+FLASH 32M {
+ SI_ALL 8M {
+ SI_DESC 16K
+ SI_ME
+ }
+ SI_BIOS 24M {
+ RW_SECTION_A 7680K {
+ VBLOCK_A 8K
+ FW_MAIN_A(CBFS)
+ RW_FWID_A 64
+ }
+ RW_MISC 1M {
+ UNIFIED_MRC_CACHE(PRESERVE) 128K {
+ RECOVERY_MRC_CACHE 64K
+ RW_MRC_CACHE 64K
+ }
+ RW_ELOG(PRESERVE) 16K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 24K
+ }
+ # This section starts at the 16M boundary in SPI flash.
+ # MTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7680K {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+ }
+ RW_LEGACY(CBFS) 1M
+ RW_UNUSED 3M
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO 4M {
+ RO_VPD(PRESERVE) 16K
+ RO_GSCVD 8K
+ RO_SECTION {
+ FMAP 2K
+ RO_FRID 64
+ GBB@4K 12K
+ COREBOOT(CBFS)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/fatcat/chromeos.c b/src/mainboard/google/fatcat/chromeos.c
new file mode 100644
index 0000000..5ed041f
--- /dev/null
+++ b/src/mainboard/google/fatcat/chromeos.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+#if CONFIG(VBOOT_LID_SWITCH)
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+#else
+ /* fake LID open to avoid shutdown in depthcharge */
+ {-1, ACTIVE_HIGH, 1, "lid"},
+#endif
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {-1, ACTIVE_HIGH, 0, "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+ return gpio_get(GPIO_PCH_WP);
+}
+
+int get_ec_is_trusted(void)
+{
+ /* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */
+ return 0;
+}
diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd
new file mode 100644
index 0000000..77f5555
--- /dev/null
+++ b/src/mainboard/google/fatcat/chromeos.fmd
@@ -0,0 +1,49 @@
+FLASH 32M {
+ SI_ALL 8M {
+ SI_DESC 16K
+ SI_ME
+ }
+ SI_BIOS 24M {
+ RW_SECTION_A 7M {
+ VBLOCK_A 8K
+ FW_MAIN_A(CBFS)
+ RW_FWID_A 64
+ }
+ RW_MISC 1M {
+ UNIFIED_MRC_CACHE(PRESERVE) 128K {
+ RECOVERY_MRC_CACHE 64K
+ RW_MRC_CACHE 64K
+ }
+ RW_ELOG(PRESERVE) 16K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 24K
+ }
+ # This section starts at the 16M boundary in SPI flash.
+ # MTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7M {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+ }
+ RW_LEGACY(CBFS) 1M
+ RW_UNUSED 4M
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO 4M {
+ RO_VPD(PRESERVE) 16K
+ RO_GSCVD 8K
+ RO_SECTION {
+ FMAP 2K
+ RO_FRID 64
+ GBB@4K 12K
+ COREBOOT(CBFS)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/fatcat/dsdt.asl b/src/mainboard/google/fatcat/dsdt.asl
new file mode 100644
index 0000000..2c714d7
--- /dev/null
+++ b/src/mainboard/google/fatcat/dsdt.asl
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <variant/ec.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725
+)
+{
+ /* TODO: Add ACPI code as per board design */
+}
diff --git a/src/mainboard/google/fatcat/ec.c b/src/mainboard/google/fatcat/ec.c
new file mode 100644
index 0000000..f828bc5
--- /dev/null
+++ b/src/mainboard/google/fatcat/ec.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+ static const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ printk(BIOS_DEBUG, "mainboard: EC init\n");
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c
new file mode 100644
index 0000000..107ee8d
--- /dev/null
+++ b/src/mainboard/google/fatcat/mainboard.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <soc/ramstage.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+ /* default implementation does nothing */
+}
+
+void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
+{
+ variant_update_soc_chip_config(config);
+}
+
+__weak void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
+{
+ /* default implementation does nothing */
+}
+
+static void mainboard_init(void *chip_info)
+{
+ struct pad_config *padbased_table;
+ const struct pad_config *base_pads;
+ size_t base_num;
+
+ padbased_table = new_padbased_table();
+ base_pads = variant_gpio_table(&base_num);
+ gpio_padbased_override(padbased_table, base_pads, base_num);
+ fw_config_gpio_padbased_override(padbased_table);
+ gpio_configure_pads_with_padbased(padbased_table);
+ free(padbased_table);
+ baseboard_devtree_update();
+}
+
+void __weak baseboard_devtree_update(void)
+{
+ /* Override dev tree settings per baseboard */
+}
+
+void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
+{
+ /* Add board-specific MS0X entries */
+ /*
+ if (s0ix_entry == S0IX_ENTRY) {
+ implement variant operations here
+ }
+ if (s0ix_entry == S0IX_EXIT) {
+ implement variant operations here
+ }
+ */
+}
+
+static void mainboard_dev_init(struct device *dev)
+{
+ mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_dev_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
new file mode 100644
index 0000000..9e41d46
--- /dev/null
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ const struct pad_config *pads;
+ size_t pads_num;
+ const struct mb_cfg *mem_config = variant_memory_params();
+ bool half_populated = variant_is_half_populated();
+ struct mem_spd spd_info;
+
+ pads = variant_romstage_gpio_table(&pads_num);
+ gpio_configure_pads(pads, pads_num);
+
+ memset(&spd_info, 0, sizeof(spd_info));
+ variant_get_spd_info(&spd_info);
+
+ memcfg_init(memupd, mem_config, &spd_info, half_populated);
+}
diff --git a/src/mainboard/google/fatcat/smihandler.c b/src/mainboard/google/fatcat/smihandler.c
new file mode 100644
index 0000000..9208d51
--- /dev/null
+++ b/src/mainboard/google/fatcat/smihandler.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/smm.h>
+#include <elog.h>
+#include <intelblocks/smihandler.h>
+#include <variant/ec.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
+
+void elog_gsmi_cb_mainboard_log_wake_source(void)
+{
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
+}
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk
new file mode 100644
index 0000000..be05cd4
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
new file mode 100644
index 0000000..9f4f3455
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -0,0 +1,3 @@
+chip soc/intel/meteorlake
+ device domain 0 on end
+end
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h
new file mode 100644
index 0000000..b9b4689
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <baseboard/gpio.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+/*
+ * EC can wake from S3/S0ix with:
+ * 1. Lid open
+ * 2. AC Connect/Disconnect
+ * 3. Power button
+ * 4. Key press
+ * 5. Mode change
+ * 6. Low battery
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
+ MAINBOARD_EC_S5_WAKE_EVENTS)
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) | \
+ MAINBOARD_EC_S3_WAKE_EVENTS)
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN))
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable Keyboard Backlight */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
+#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
+
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
new file mode 100644
index 0000000..67eb97f
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* FIXME: update below code as per board schematics */
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI 0
+/* GPIO IRQ for tight timestamps / wake support */
+#define EC_SYNC_IRQ 0
+/* WP signal to PCH */
+#define GPIO_PCH_WP 0
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c
new file mode 100644
index 0000000..4f621f3
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-3.0-or-later */
+
+#include <baseboard/variants.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+ .type = MEM_TYPE_LP5X,
+
+ /* TODO: Add Memory configuration */
+ .ect = 1, /* Early Command Training */
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+ return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+ return 0;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+ return 0;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+ spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+ spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..8a97d00
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <chip.h>
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of entries for
+ * each table.
+ */
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_romstage_gpio_table(size_t *num);
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
+
+const struct mb_cfg *variant_memory_params(void);
+void variant_get_spd_info(struct mem_spd *spd_info);
+int variant_memory_sku(void);
+bool variant_is_half_populated(void);
+void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config);
+
+/* Get soc power limit config struct for current CPU sku */
+struct soc_power_limits_config *variant_get_soc_power_limit_config(void);
+
+enum s0ix_entry {
+ S0IX_EXIT,
+ S0IX_ENTRY,
+};
+
+void variant_generate_s0ix_hook(enum s0ix_entry entry);
+
+/* Modify devictree settings during ramstage by baseboard */
+void baseboard_devtree_update(void);
+/* Modify devictree settings during ramstage by dedicated variant */
+void variant_devtree_update(void);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
new file mode 100644
index 0000000..91f031e
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
new file mode 100644
index 0000000..ebb0120
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* This header block is used to supply information to arbitrage, a
+ * google-internal tool. Updating it incorrectly will lead to issues,
+ * so please don't update it unless a change is specifically required.
+ * BaseID: 3EC4CE58201758F4
+ * Overrides: c826ba419f06f9df9cded8e60633253ddc7b60ff
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+ /* TODO: Fill gpio configuration */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* TODO: Fill gpio configuration */
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+ /* TODO: Fill gpio configuration */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(romstage_gpio_table);
+ return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h b/src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h
new file mode 100644
index 0000000..4fc0622
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h
new file mode 100644
index 0000000..e468198
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* TODO: Add GPIO as per fatcat board */
+
+#endif /* __MAINBOARD_GPIO_H__ */