tree 30caeb3eb226ad24492c3774903dead276e808fb
parent c4ca2f63967c3ab274d068d50f98df584014101a
author Raul E Rangel <rrangel@chromium.org> 1623267370 -0600
committer Felix Held <felix-coreboot@felixheld.de> 1626093033 +0000

soc/amd/{cezanne,common}: Enable IOMMU PCIe Device

This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.

BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>