mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
TEST=Able to pass MRC training on DDR4/5 SKUs
Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index cab4ef9..5d374db 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -12,7 +12,7 @@
/* Baseboard Rcomp target values */
.rcomp_targets = {40, 30, 33, 33, 30},
- .dq_pins_interleaved = true,
+ .dq_pins_interleaved = false,
.ect = true, /* Early Command Training */
@@ -61,7 +61,7 @@
/* Baseboard Rcomp target values */
.rcomp_targets = {50, 30, 30, 30, 27},
- .dq_pins_interleaved = true,
+ .dq_pins_interleaved = false,
.ect = true, /* Early Command Training */