commit 3a5217a77b2561eb122d881581119753f2cd0039
author Tim Crawford <tcrawford@system76.com> Tue Jul 26 14:04:04 2022 -0600
committer Martin Roth <martin.roth@amd.corp-partner.google.com> Fri Aug 19 14:23:24 2022 +0000
tree db86b34f6816a0147fdd68112e1dead75e7899ce
parent 34c8a19f9272c7483c4f6a009e59ef748625f25a

mb/system76/gaze16: Configure GPIOs in mainboard_init()

Configure GPIOs in `mainboard_init()` instead of during FSP config.

Change-Id: Icc40ce71d2bd104c5f41e992f9b28824a3b734d6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66169
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/system76/gaze16/ramstage.c

diff --git a/src/mainboard/system76/gaze16/ramstage.c b/src/mainboard/system76/gaze16/ramstage.c
index 6963771..480c49c 100644
--- a/src/mainboard/system76/gaze16/ramstage.c
+++ b/src/mainboard/system76/gaze16/ramstage.c
@@ -2,13 +2,12 @@
 
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
-#include "variant.h"
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+static void mainboard_init(void *chip_info)
 {
-	variant_silicon_init_params(params);
-
-	params->PchLegacyIoLowLatency = 1;
-
 	variant_configure_gpios();
 }
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/gaze16/variant.h

diff --git a/src/mainboard/system76/gaze16/variant.h b/src/mainboard/system76/gaze16/variant.h
index dcf2e38..1f66112 100644
--- a/src/mainboard/system76/gaze16/variant.h
+++ b/src/mainboard/system76/gaze16/variant.h
@@ -6,6 +6,5 @@
 #include <fsp/soc_binding.h>
 
 void variant_memory_init_params(FSPM_UPD *mupd);
-void variant_silicon_init_params(FSP_S_CONFIG *params);
 
 #endif

src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c

diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c
index 426ae84..9d98563 100644
--- a/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "../../variant.h"
+#include <soc/ramstage.h>
 
-void variant_silicon_init_params(FSP_S_CONFIG *params)
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
+	params->PchLegacyIoLowLatency = 1;
+
 	// PEG0 Config
 	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
 	params->CpuPcieRpLtrEnable[0] = 1;

src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c

diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c
index 7422613..0f83461 100644
--- a/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "../../variant.h"
+#include <soc/ramstage.h>
 
-void variant_silicon_init_params(FSP_S_CONFIG *params)
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
+	params->PchLegacyIoLowLatency = 1;
+
 	// PEG0 Config
 	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
 	params->CpuPcieRpLtrEnable[0] = 1;