commit 39e1f44f331040b2e9574e9c792f583b8c6a5aba
author Gaggery Tsai <gaggery.tsai@intel.com> Wed Jan 08 15:22:13 2020 -0800
committer Nico Huber <nico.h@gmx.de> Sat Jan 18 12:03:17 2020 +0000
tree 96b3a479ae3107442e01c612eaf588dee0759daa
parent 06a078a06723ec5c085b6a8df3adee98e6171b5f

soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs

This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for
10-Core ID.

Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/cannonlake/bootblock/report_platform.c

diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 19dce00..67dd452 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -83,6 +83,8 @@
 	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_4, "CometLake-S G0/G1 (4+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_2, "CometLake-S G0/G1 (2+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_H_4_2, "CometLake-H (4+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" },