diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index aced71c..41c0e9f 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -48,9 +48,6 @@
 	RCBA16(D28IR) = 0x3201;
 	RCBA16(D27IR) = 0x3216;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Disable unused devices */
 	RCBA32(FD) |= FD_INTLAN;
 
@@ -61,35 +58,6 @@
 	RCBA32(0x1e98) = 0x000c0801;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	/* program secondary mlt XXX byte? */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	/* reset rtc power status */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	/* usb transient disconnect */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
@@ -111,6 +79,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -123,9 +92,6 @@
 
 	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 3287b76..0cc38a0 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -98,42 +98,9 @@
 
 static void rcba_config(void)
 {
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Enable PCIe Root Port Clock Gate */
 	RCBA32(CG) = 0x00000001;
 }
-
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0, boot_mode = 0;
@@ -157,6 +124,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -179,9 +147,6 @@
 
 	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index e27194aa..8c41190 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -143,9 +143,6 @@
 	RCBA16(D28IR) = 0x3201;
 	RCBA16(D27IR) = 0x3216;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Disable unused devices */
 	RCBA32(FD) |= FD_INTLAN;
 
@@ -162,35 +159,6 @@
 	RCBA32(0x1e98) = 0x000c0801;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
@@ -211,6 +179,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	setup_special_ich7_gpios();
@@ -225,9 +194,6 @@
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 9a9e947..cd13451 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -58,42 +58,10 @@
 
 static void rcba_config(void)
 {
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Enable PCIe Root Port Clock Gate */
 	RCBA32(CG) = 0x00000001;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0, boot_mode = 0;
@@ -118,6 +86,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -130,9 +99,6 @@
 
 	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index fd258af..47e28a8 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -120,42 +120,10 @@
 	RCBA16(D28IR) = 0x3201;
 	RCBA16(D27IR) = 0x0146;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Enable PCIe Root Port Clock Gate */
 	// RCBA32(0x341c) = 0x00000001;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
@@ -175,6 +143,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -187,9 +156,6 @@
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index ba01379..ada6e61 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -40,9 +40,6 @@
 	RCBA16(D28IR) = 0x3201;
 	RCBA16(D27IR) = 0x0146;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Disable unused devices */
 	RCBA32(FD) |= FD_INTLAN;
 
@@ -50,35 +47,6 @@
 	// RCBA32(0x341c) = 0x00000001;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0, boot_mode = 0;
@@ -101,6 +69,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -113,9 +82,6 @@
 
 	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index cb01046..d67a60b 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -165,40 +165,7 @@
 	RCBA16(D28IR) = 0x3210;
 	RCBA16(D27IR) = 0x3210;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Enable PCIe Root Port Clock Gate */
-
-}
-
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	/* program secondary mlt XXX byte? */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	/* reset rtc power status */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	/* usb transient disconnect */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)
@@ -221,6 +188,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -233,9 +201,6 @@
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index ac78aae..ab49e6e 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -76,9 +76,6 @@
 	RCBA16(D28IR) = 0x7654;
 	RCBA16(D27IR) = 0x0010;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Disable unused devices */
 	RCBA32(FD) |= FD_INTLAN;
 
@@ -89,35 +86,6 @@
 	RCBA64(IOTR3) = 0x000200f0000c0801ULL;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
@@ -126,15 +94,13 @@
 
 	enable_lapic();
 
+	/* Set up GPIO's early since it is needed for dock init */
+	i82801gx_setup_bars();
+	setup_pch_gpios(&mainboard_gpio_map);
+
 	i82801gx_lpc_setup();
 	mb_lpc_decode();
 
-	/* We want early GPIO setup, to be able to detect legacy I/O module */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
-	/* Enable GPIOs */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10);
-	setup_pch_gpios(&mainboard_gpio_map);
-
 	dock_err = dlpc_init();
 
 	/* We prefer Legacy I/O module over docking */
@@ -156,6 +122,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -168,9 +135,6 @@
 
 	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1008bb0..6eeb2d1 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -77,9 +77,6 @@
 	RCBA16(D28IR) = 0x7654;
 	RCBA16(D27IR) = 0x0010;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Disable unused devices */
 	RCBA32(FD) |= FD_INTLAN;
 
@@ -90,35 +87,6 @@
 	RCBA64(IOTR3) = 0x000200f0000c0801ULL;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
@@ -126,9 +94,8 @@
 
 	enable_lapic();
 
-	/* Enable GPIOs */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10);  /* 0x4c == GC */
+	/* Set up GPIO's early since it is needed for dock init */
+	i82801gx_setup_bars();
 	setup_pch_gpios(&mainboard_gpio_map);
 
 	i82801gx_lpc_setup();
@@ -161,6 +128,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	s3resume = southbridge_detect_s3_resume();
@@ -173,9 +141,6 @@
 
 	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 019ec1b..f1a638d 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -108,9 +108,6 @@
 	RCBA16(D28IR) = 0x3201;
 	RCBA16(D27IR) = 0x3216;
 
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
-
 	/* Disable unused devices */
 	RCBA32(FD) |= FD_INTLAN;
 
@@ -125,35 +122,6 @@
 	RCBA32(0x1e98) = 0x000c0801;
 }
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-
-	/* program secondary mlt XXX byte? */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
-	/* reset rtc power status */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
-	/* usb transient disconnect */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	ich7_setup_cir();
-}
-
 static void init_artec_dongle(void)
 {
 	/* Enable 4MB decoding */
@@ -181,6 +149,7 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	i945_early_initialization();
 
 	/* This has to happen after i945_early_initialization() */
@@ -196,9 +165,6 @@
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
 	 */
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index a5bfe6f..13dce61 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,7 +23,6 @@
 #include <cbmem.h>
 #include <romstage_handoff.h>
 #include <pc80/mc146818rtc.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 
 #include "i945.h"
@@ -156,21 +155,6 @@
 	if (i945_silicon_revision() == 0)
 		printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
 
-	/* Setting up Southbridge. In the northbridge code. */
-	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-
-	i82801gx_setup_bars();
-
-	setup_pch_gpios(&mainboard_gpio_map);
-	printk(BIOS_DEBUG, " done.\n");
-
-	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
-	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	outw((1 <<  3), DEFAULT_PMBASE | 0x60 | 0x04);	/* clear timeout */
-	outw((1 <<  1), DEFAULT_PMBASE | 0x60 | 0x06);	/* clear 2nd timeout */
-	printk(BIOS_DEBUG, " done.\n");
-
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	/* Set up all hardcoded northbridge BARs */
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 3a9df51..6698fa8 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -136,8 +136,6 @@
 	pci_write_config8(LPC, 0x8, 0x0);
 	RCBA32(0x3410) = 0x00020465;
 
-	ich7_setup_cir();
-
 	pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
 	pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
 	pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
@@ -156,22 +154,6 @@
 
 static void pineview_setup_bars(void)
 {
-	/* Setting up Southbridge. In the northbridge code. */
-	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-
-	i82801gx_setup_bars();
-
-	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
-	printk(BIOS_DEBUG, " done.\n");
-
-	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
-	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	printk(BIOS_DEBUG, " done.\n");
-
-	/* Enable upper 128bytes of CMOS */
-	RCBA32(0x3400) = (1 << 2);
-
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	pci_write_config8(D0F0, 0x8, 0x69);
 
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index e60738c..e324c05 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -24,7 +24,6 @@
 #include <cf9_reset.h>
 #include <romstage_handoff.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <arch/romstage.h>
 #include <cpu/x86/lapic.h>
@@ -36,9 +35,6 @@
 	/* Set up virtual channel 0 */
 	RCBA32(0x0014) = 0x80000001;
 	RCBA32(0x001c) = 0x03128010;
-
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
 }
 
 __weak void mb_pirq_setup(void)
@@ -55,17 +51,12 @@
 
 	enable_lapic();
 
-	/* Enable GPIOs */
-	pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
-
-	setup_pch_gpios(&mainboard_gpio_map);
-
 	enable_smbus();
 
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	pineview_early_initialization();
 
 	post_code(0x30);
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index 7f5f442..0bd6198 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -12,7 +12,10 @@
  */
 
 #include <stdint.h>
+#include <console/console.h>
 #include <device/pci_ops.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmbase.h>
 #include "i82801gx.h"
 #include "chip.h"
 
@@ -62,3 +65,53 @@
 	pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1);
 	pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
 }
+
+#define TCO_BASE 0x60
+
+#if ENV_ROMSTAGE
+void i82801gx_early_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+	/* Setting up Southbridge. In the northbridge code. */
+	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
+	i82801gx_setup_bars();
+
+	setup_pch_gpios(&mainboard_gpio_map);
+	printk(BIOS_DEBUG, " done.\n");
+
+	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
+	write_pmbase16(TCO_BASE + 0x8, (1 << 11));	/* halt timer */
+	write_pmbase16(TCO_BASE + 0x4, (1 << 3));	/* clear timeout */
+	write_pmbase16(TCO_BASE + 0x6, (1 << 1));	/* clear 2nd timeout */
+	printk(BIOS_DEBUG, " done.\n");
+
+	/* program secondary mlt XXX byte? */
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
+
+	/* reset rtc power status */
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+	reg8 &= ~RTC_BATTERY_DEAD;
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+
+	/* usb transient disconnect */
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	/* Enable IOAPIC */
+	RCBA8(OIC) = 0x03;
+	RCBA8(OIC);
+
+	ich7_setup_cir();
+}
+#endif
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 9eea262..3d27faa 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -42,6 +42,7 @@
 void enable_smbus(void);
 void i82801gx_lpc_setup(void);
 void i82801gx_setup_bars(void);
+void i82801gx_early_init(void);
 
 #if ENV_ROMSTAGE
 int smbus_read_byte(unsigned int device, unsigned int address);