diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index a5bfe6f..13dce61 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,7 +23,6 @@
 #include <cbmem.h>
 #include <romstage_handoff.h>
 #include <pc80/mc146818rtc.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 
 #include "i945.h"
@@ -156,21 +155,6 @@
 	if (i945_silicon_revision() == 0)
 		printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
 
-	/* Setting up Southbridge. In the northbridge code. */
-	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-
-	i82801gx_setup_bars();
-
-	setup_pch_gpios(&mainboard_gpio_map);
-	printk(BIOS_DEBUG, " done.\n");
-
-	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
-	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	outw((1 <<  3), DEFAULT_PMBASE | 0x60 | 0x04);	/* clear timeout */
-	outw((1 <<  1), DEFAULT_PMBASE | 0x60 | 0x06);	/* clear 2nd timeout */
-	printk(BIOS_DEBUG, " done.\n");
-
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	/* Set up all hardcoded northbridge BARs */
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 3a9df51..6698fa8 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -136,8 +136,6 @@
 	pci_write_config8(LPC, 0x8, 0x0);
 	RCBA32(0x3410) = 0x00020465;
 
-	ich7_setup_cir();
-
 	pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
 	pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
 	pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
@@ -156,22 +154,6 @@
 
 static void pineview_setup_bars(void)
 {
-	/* Setting up Southbridge. In the northbridge code. */
-	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-
-	i82801gx_setup_bars();
-
-	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
-	printk(BIOS_DEBUG, " done.\n");
-
-	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
-	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	printk(BIOS_DEBUG, " done.\n");
-
-	/* Enable upper 128bytes of CMOS */
-	RCBA32(0x3400) = (1 << 2);
-
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	pci_write_config8(D0F0, 0x8, 0x69);
 
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index e60738c..e324c05 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -24,7 +24,6 @@
 #include <cf9_reset.h>
 #include <romstage_handoff.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <arch/romstage.h>
 #include <cpu/x86/lapic.h>
@@ -36,9 +35,6 @@
 	/* Set up virtual channel 0 */
 	RCBA32(0x0014) = 0x80000001;
 	RCBA32(0x001c) = 0x03128010;
-
-	/* Enable IOAPIC */
-	RCBA8(OIC) = 0x03;
 }
 
 __weak void mb_pirq_setup(void)
@@ -55,17 +51,12 @@
 
 	enable_lapic();
 
-	/* Enable GPIOs */
-	pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
-
-	setup_pch_gpios(&mainboard_gpio_map);
-
 	enable_smbus();
 
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
+	i82801gx_early_init();
 	pineview_early_initialization();
 
 	post_code(0x30);