diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index d55741f..c1fe5a7 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -12,6 +12,7 @@
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 #include "../chip.h"
@@ -29,7 +30,8 @@
 	 * Probe for no IGD and disable InternalGfx and panel power to prevent a
 	 * crash in FSP-M.
 	 */
-	if (dev && dev->enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
+	const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
+	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
 		/* Set IGD stolen size to 64MB. */
 		m_cfg->InternalGfx = 1;
 		m_cfg->IgdDvmt50PreAlloc = 2;
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 0801da2..a5311d9 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -16,8 +16,8 @@
 	const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	uint32_t mask = 0;
 
-	if (!dev || !dev->enabled) {
-		/* Skip IGD initialization in FSP if device is disabled in devicetree.cb. */
+	if (CONFIG(SOC_INTEL_DISABLE_IGD) || !dev || !dev->enabled) {
+		/* Skip IGD initialization in FSP if device is disabled */
 		m_cfg->InternalGfx = 0;
 		m_cfg->IgdDvmt50PreAlloc = 0;
 	} else {
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index cd70807..7100232 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -22,7 +22,7 @@
 	 * Otherwise, skip IGD init in FSP.
 	 */
 	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	m_cfg->InternalGfx = is_dev_enabled(dev);
+	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev);
 	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
 
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index 2793c2d..6c6e2e6 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -112,7 +112,7 @@
 	const struct device *dev;
 
 	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	m_cfg->InternalGfx = dev && dev->enabled;
+	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
 
 	/*
 	 * If iGPU is enabled, set IGD stolen size to 64MB. The FBC