soc/intel/cmn/pcie: Allow SoC to overwrite snoop/non-snoop latency
The Intel SoC Meteor Lake requires a higher pcie max non-snoop and
snoop latency tolerance. Add config to let SoC overwrite the common
code settings if needed.
BUG=none
TEST=Boot google/rex and print/check if able to overwrite values.
Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig
index 859ba22..f65d8c1 100644
--- a/src/soc/intel/common/block/pcie/Kconfig
+++ b/src/soc/intel/common/block/pcie/Kconfig
@@ -17,6 +17,18 @@
config PCIEXP_L1_SUB_STATE
default y
+config PCIE_LTR_MAX_SNOOP_LATENCY
+ hex
+ default 0x1003
+ help
+ Latency tolerance reporting, max snoop latency value defaults to 3.14 ms.
+
+config PCIE_LTR_MAX_NO_SNOOP_LATENCY
+ hex
+ default 0x1003
+ help
+ Latency tolerance reporting, max non-snoop latency value defaults to 3.14 ms.
+
endif # SOC_INTEL_COMMON_BLOCK_PCIE
config PCIE_DEBUG_INFO
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index c8a958d..d5d3322 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -48,8 +48,8 @@
static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop)
{
- *max_snoop = PCIE_LTR_MAX_SNOOP_LATENCY_3146US;
- *max_nosnoop = PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US;
+ *max_snoop = CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY;
+ *max_nosnoop = CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY;
}
static struct pci_operations pcie_ops = {