commit 38fcf40330adbbb3b93c29eb809a9a56504a63a5
author Curtis Chen <curtis.chen@intel.com> Wed Jan 19 16:36:31 2022 +0800
committer Felix Held <felix-coreboot@felixheld.de> Fri Jan 21 16:06:26 2022 +0000
tree 11e15884f033d92bc0d79d5f3f92018ca0048452
parent 77426ffa6c056d37b5a3b833051ae2f720bde597

soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR config

ADL-P 2+8+2 (28W) would have a match PD to ADL-P 4+8+2 (28W). Group them
into the same group core "ADL_P_282_482_28W_CORE".

BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I3f92c0f5d717dd33ac478fbaa883f3e972e7a7de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/alderlake/chip.h

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 93d8eee..e997e78 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -22,7 +22,7 @@
 /* Types of different SKUs */
 enum soc_intel_alderlake_power_limits {
 	ADL_P_142_242_282_15W_CORE,
-	ADL_P_482_28W_CORE,
+	ADL_P_282_482_28W_CORE,
 	ADL_P_682_28W_CORE,
 	ADL_P_442_482_45W_CORE,
 	ADL_P_642_682_45W_CORE,
@@ -51,7 +51,8 @@
 	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
 	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
 	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_28W_CORE, TDP_28W },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W },
 	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
 	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
 	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },