tree 6f8886194ed3b818f282813829c77a010bddffbb
parent 69d5bbf073ee45f18492a6204dc25c934c6d3c05
author Weiyi Lu <weiyi.lu@mediatek.com> 1588734315 +0800
committer Patrick Georgi <pgeorgi@google.com> 1589359100 +0000

soc/mediatek: improve ca53 frequency change procedure

To change frequency, the SOC PLL team suggests procedure below:
First, we need to enable the intermediate clock and
switch the ca53 clock source to the intermediate clock.
Second, disable the armpll_ll clock output.
Third, raise armpll_ll frequency and enable the clock output.
The last, switch the ca53 clock source back to armpll_ll and
disable the intermediate clock.

BUG=b:154451241
BRANCH=jacuzzi
TEST=Boots correctly on Jacuzzi.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ib9556ba340da272fb62588f45851c93373cfa919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41077
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>