tree 8ca0f437e57a43d88375f9d5da5e5226c590d89e
parent 8a18bd8500fee7c43e257d3dfd1cc3f7db82c88c
author Arthur Heymans <arthur@aheymans.xyz> 1622470205 +0200
committer Werner Zeh <werner.zeh@siemens.com> 1623817116 +0000

soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them

Move locking CPU MSRs during CPU init instead of using
CONFIG_PARALLEL_MP_AP_WORK functions.

The AES Lock enable bit caused CPU exception errors as this should not
run on HT siblings. The set_aesni_lock() function takes care of that.

Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55098
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>