mb/google/brox: Fix GPE_EC_WAKE configuration
Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE
corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration.
BUG=b:329026602
TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up
using EC generated events like AC connect/disconnect.
Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h
index a027b4c..d049865 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h
+++ b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h
@@ -74,7 +74,6 @@
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
-#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
-#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
+#define EC_ENABLE_SYNC_IRQ /* Enable EC Sync IRQ defined in baseboard/gpio.h */
#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
index 0e69fb3..2c1fc0a 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
+++ b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
@@ -8,13 +8,13 @@
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
-/* EC wake is EC_PCH_INT which is routed to GPP_D0 pin */
-#define GPE_EC_WAKE GPE0_DW1_00
+/* EC wake is EC_PCH_WAKE which is routed to GPP_D1 pin */
+#define GPE_EC_WAKE GPE0_DW1_01
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E8
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_D17
-/* GPIO IRQ for tight timestamps / wake support */
+/* GPIO IRQ for tight timestamps, MKBP interrupts */
#define EC_SYNC_IRQ GPP_D0_IRQ
#endif /* __BASEBOARD_GPIO_H__ */