soc/intel/meteorlake: Add ASPM setting in pcie_rp_config
This change provides config for devicetree to control ASPM per port
TEST=Build and Boot verified on google/rex
Port of 'commit 6e52c1da4a22 ("soc/intel/{adl,common}:
Add ASPM setting in pcie_rp_config)'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index ad6db10..d40779a 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -93,6 +93,21 @@
return ctl - 1;
}
+/*
+ * get_aspm_control() ensures that the right UPD value is set in fsp_params.
+ * 0: Disable ASPM
+ * 1: L0s only
+ * 2: L1 only
+ * 3: L0s and L1
+ * 4: Auto configuration
+ */
+static unsigned int get_aspm_control(enum ASPM_control ctl)
+{
+ if (ctl > ASPM_AUTO)
+ ctl = ASPM_AUTO;
+ return ctl;
+}
+
__weak void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
{
/* Override settings per board. */
@@ -393,6 +408,8 @@
s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+ if (rp_cfg->pcie_rp_aspm)
+ s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
}
s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
}