ec/google/chromec: Add DPTC support for host event 1/2/9
DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for
host event lid-open/lid-close/Thermal Threshold.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index e4637b3..7c252e6 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -229,6 +229,11 @@
Method (_Q01, 0, NotSerialized)
{
Printf ("EC: LID CLOSE")
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+ If (CondRefOf (\_SB.DPTC)) {
+ \_SB.DPTC()
+ }
+#endif
Store (LIDS, \LIDS)
#ifdef EC_ENABLE_LID_SWITCH
Notify (LID0, 0x80)
@@ -239,6 +244,11 @@
Method (_Q02, 0, NotSerialized)
{
Printf ("EC: LID OPEN")
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+ If (CondRefOf (\_SB.DPTC)) {
+ \_SB.DPTC()
+ }
+#endif
Store (LIDS, \LIDS)
Notify (CREC, 0x2)
#ifdef EC_ENABLE_LID_SWITCH
@@ -540,6 +550,12 @@
*/
Method (_Q09, 0, NotSerialized)
{
+
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+ If (CondRefOf (\_SB.DPTC)) {
+ \_SB.DPTC()
+ }
+#endif
If (!Acquire (^PATM, 1000)) {
/* Read sensor ID for event */
Store (^PATI, Local0)