diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index aa3505f..1a68289 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -97,6 +97,93 @@
 		char *name;
 	} msr_entry_t;
 
+	/* Pentium III */
+	static const msr_entry_t model67x_global_msrs[] = {
+		{ 0x0000, "IA32_P5_MC_ADDR" },
+		{ 0x0001, "IA32_P5_MC_TYPE" },
+		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
+		{ 0x0017, "IA32_PLATFORM_ID" },
+		{ 0x001b, "IA32_APIC_BASE" },
+		{ 0x002a, "EBL_CR_POWERON" },
+		{ 0x0033, "TEST_CTL" },
+		//{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
+		{ 0x0088, "BBL_CR_D0" },
+		{ 0x0089, "BBL_CR_D1" },
+		{ 0x008a, "BBL_CR_D2" },
+		{ 0x008b, "IA32_BIOS_SIGN_ID" },
+		{ 0x00c1, "PERFCTR0" },
+		{ 0x00c2, "PERFCTR1" },
+		{ 0x00fe, "IA32_MTRRCAP" },
+		{ 0x0116, "BBL_CR_ADDR" },
+		{ 0x0118, "BBL_CR_DECC" },
+		{ 0x0119, "BBL_CR_CTL" },
+		//{ 0x011a, "BBL_CR_TRIG" },
+		{ 0x011b, "BBL_CR_BUSY" },
+		{ 0x011e, "BBL_CR_CTL3" },
+		{ 0x0174, "IA32_SYSENTER_CS" },
+		{ 0x0175, "IA32_SYSENTER_ESP" },
+		{ 0x0176, "IA32_SYSENTER_EIP" },
+		{ 0x0179, "IA32_MCG_CAP" },
+		{ 0x017a, "IA32_MCG_STATUS" },
+		{ 0x017b, "IA32_MCG_CTL" },
+		{ 0x0186, "IA32_PERF_EVNTSEL0" },
+		{ 0x0187, "IA32_PERF_EVNTSEL1" },
+		{ 0x01d9, "IA32_DEBUGCTL" },
+		{ 0x01db, "MSR_LASTBRANCHFROMIP" },
+		{ 0x01dc, "MSR_LASTBRANCHTOIP" },
+		{ 0x01dd, "MSR_LASTINTFROMIP" },
+		{ 0x01de, "MSR_LASTINTTOIP" },
+		{ 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" },
+		{ 0x0200, "IA32_MTRR_PHYSBASE0" },
+		{ 0x0201, "IA32_MTRR_PHYSMASK0" },
+		{ 0x0202, "IA32_MTRR_PHYSBASE1" },
+		{ 0x0203, "IA32_MTRR_PHYSMASK1" },
+		{ 0x0204, "IA32_MTRR_PHYSBASE2" },
+		{ 0x0205, "IA32_MTRR_PHYSMASK2" },
+		{ 0x0206, "IA32_MTRR_PHYSBASE3" },
+		{ 0x0207, "IA32_MTRR_PHYSMASK3" },
+		{ 0x0208, "IA32_MTRR_PHYSBASE4" },
+		{ 0x0209, "IA32_MTRR_PHYSMASK4" },
+		{ 0x020a, "IA32_MTRR_PHYSBASE5" },
+		{ 0x020b, "IA32_MTRR_PHYSMASK5" },
+		{ 0x020c, "IA32_MTRR_PHYSBASE6" },
+		{ 0x020d, "IA32_MTRR_PHYSMASK6" },
+		{ 0x020e, "IA32_MTRR_PHYSBASE7" },
+		{ 0x020f, "IA32_MTRR_PHYSMASK7" },
+		{ 0x0250, "IA32_MTRR_FIX64K_00000" },
+		{ 0x0258, "IA32_MTRR_FIX16K_80000" },
+		{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
+		{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
+		{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
+		{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
+		{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
+		{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
+		{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
+		{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
+		{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
+		{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
+		{ 0x0400, "IA32_MC0_CTL" },
+		{ 0x0401, "IA32_MC0_STATUS" },
+		{ 0x0402, "IA32_MC0_ADDR" },
+		//{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
+		{ 0x0404, "IA32_MC1_CTL" },
+		{ 0x0405, "IA32_MC1_STATUS" },
+		{ 0x0406, "IA32_MC1_ADDR" },
+		//{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO
+		{ 0x0408, "IA32_MC2_CTL" },
+		{ 0x0409, "IA32_MC2_STATUS" },
+		{ 0x040a, "IA32_MC2_ADDR" },
+		//{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO
+		{ 0x040c, "IA32_MC4_CTL" },
+		{ 0x040d, "IA32_MC4_STATUS" },
+		{ 0x040e, "IA32_MC4_ADDR" },
+		//{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
+		{ 0x0410, "IA32_MC3_CTL" },
+		{ 0x0411, "IA32_MC3_STATUS" },
+		{ 0x0412, "IA32_MC3_ADDR" },
+		//{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO
+	};
+
 	static const msr_entry_t model6bx_global_msrs[] = {
 		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
 		{ 0x0017, "IA32_PLATFORM_ID" },
@@ -453,6 +540,7 @@
 	} cpu_t;
 
 	cpu_t cpulist[] = {
+		{ 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
 		{ 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
 		{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
 		{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },