commit 351f1e68c45f4f092399bff6a4673b0e8d1d6f50
author Maulik V Vaghela <maulik.v.vaghela@intel.com> Thu May 13 11:34:14 2021 +0530
committer Patrick Georgi <pgeorgi@google.com> Fri May 14 09:03:01 2021 +0000
tree 7e4fb8828f9f838d35674324e46f825bee5eab00
parent 6e97ac76f336baff4caf3b2a4cbb1f5df551c06f

soc/intel/alderlake: Update CPU and IGD Device IDs

Updated CPU ID and IGD ID for Alder Lake as per EDS.

TEST=Code compilation works and coreboot is able to boot and identify
new device Ids.

Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/alderlake/bootblock/report_platform.c

diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 2666426..78f02ec 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -23,6 +23,7 @@
 	const char *name;
 } cpu_table[] = {
 	{ CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" },
+	{ CPUID_ALDERLAKE_P_B0, "Alderlake-P B0" },
 	{ CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" },
 };
 
@@ -98,6 +99,7 @@
 	{ PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" },
 	{ PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" },
 	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" },
 	{ PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
 };