drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_" prefix.
1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.
For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.
Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.
Additionally, fixed SoC configs inclusion order alphabetically.
BUG=b:211954778
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index c0c500d..81cf974 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -72,6 +72,9 @@
select SOC_AMD_COMMON_FSP_PCI
select SSE2
select UDK_2017_BINDING
+ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
+ select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index b2ebabb..84af18c 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -9,23 +9,30 @@
config CPU_SPECIFIC_OPTIONS
def_bool y
+ select ACPI_SOC_NVS
+ select ADD_FSP_BINARIES if USE_AMD_BLOBS
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_X86
- select RESET_VECTOR_IN_RAM
- select X86_AMD_FIXED_MTRRS
- select X86_INIT_NEED_1_SIPI
- select ACPI_SOC_NVS
- select ADD_FSP_BINARIES if USE_AMD_BLOBS
+ select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select DRIVERS_I2C_DESIGNWARE
select DRIVERS_USB_PCI_XHCI
+ select FSP_COMPRESS_FSP_M_LZMA
+ select FSP_COMPRESS_FSP_S_LZMA
select GENERIC_GPIO_LIB
- select IDT_IN_EVERY_STAGE
select HAVE_ACPI_TABLES
+ select HAVE_CF9_RESET
select HAVE_EM100_SUPPORT
+ select HAVE_SMI_HANDLER
+ select IDT_IN_EVERY_STAGE
+ select PARALLEL_MP_AP_WORK
+ select PLATFORM_USES_FSP2_0
+ select PROVIDES_ROM_SHARING
+ select RESET_VECTOR_IN_RAM
+ select RTC
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACP_GEN1
select SOC_AMD_COMMON_BLOCK_ACPI
@@ -61,17 +68,13 @@
select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_UCODE
select SOC_AMD_COMMON_FSP_DMI_TABLES
- select PROVIDES_ROM_SHARING
- select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
- select PARALLEL_MP_AP_WORK
- select HAVE_SMI_HANDLER
select SSE2
- select RTC
- select PLATFORM_USES_FSP2_0
- select FSP_COMPRESS_FSP_M_LZMA
- select FSP_COMPRESS_FSP_S_LZMA
select UDK_2017_BINDING
- select HAVE_CF9_RESET
+ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
+ select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+ select X86_AMD_FIXED_MTRRS
+ select X86_INIT_NEED_1_SIPI
config ARCH_ALL_STAGES_X86
default n
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 96323db..1be53b5 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -76,6 +76,9 @@
select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
select SSE2
select UDK_2017_BINDING
+ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
+ select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI