tree c220499174fd38acba874f4f05093c8e11e4b681
parent 28ac0fd2f094875bd81afd8cb96f08e0cf71d2c7
author Bora Guvendik <bora.guvendik@intel.com> 1678742850 -0700
committer Subrata Banik <subratabanik@google.com> 1680595715 +0000

soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table

Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table.

990:CSME ROM started execution                        0
944:CSE sent 'Boot Stall Done' to PMC                 47,000
945:CSE started to handle ICC configuration           225,000 (178,000)
946:CSE sent 'Host BIOS Prep Done' to PMC             225,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC   516,000 (291,000)
991:Die Management Unit (DMU) load completed          587,000 (71,000)
  0:1st timestamp                                     597,427 (10,427)

BUG=b:259366109
TEST=Able to see TS elapse prior to IA reset on Rex

Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>