sb/intel/i82801jx: Add correct PCI ids and change names
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index 99dd1aa..d05e32e 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -38,6 +38,6 @@
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
- default "southbridge/intel/i82801ix/bootblock.c"
+ default "southbridge/intel/i82801jx/bootblock.c"
endif
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc
index 975a068..9121c3d 100644
--- a/src/southbridge/intel/i82801jx/Makefile.inc
+++ b/src/southbridge/intel/i82801jx/Makefile.inc
@@ -16,7 +16,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y)
-ramstage-y += i82801ix.c
+ramstage-y += i82801jx.c
ramstage-y += pci.c
ramstage-y += lpc.c
ramstage-y += pcie.c
@@ -36,8 +36,6 @@
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += early_init.c
romstage-y += early_smbus.c
-romstage-y += dmi_setup.c
endif
diff --git a/src/southbridge/intel/i82801jx/acpi/audio.asl b/src/southbridge/intel/i82801jx/acpi/audio.asl
index b09f2af..afae905 100644
--- a/src/southbridge/intel/i82801jx/acpi/audio.asl
+++ b/src/southbridge/intel/i82801jx/acpi/audio.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-/* Intel i82801I HDA */
+/* Intel i82801L HDA */
// Intel High Definition Audio (Azalia) 0:1b.0
diff --git a/src/southbridge/intel/i82801jx/acpi/ich9.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl
similarity index 95%
rename from src/southbridge/intel/i82801jx/acpi/ich9.asl
rename to src/southbridge/intel/i82801jx/acpi/ich10.asl
index 143ecb1..da8b789 100644
--- a/src/southbridge/intel/i82801jx/acpi/ich9.asl
+++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl
@@ -27,7 +27,7 @@
TRP0, 8 // IO-Trap at 0x808
}
- // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
+ // ICH10 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
Field(PMIO, ByteAcc, NoLock, Preserve)
{
@@ -42,7 +42,7 @@
}
// FIXME: purposes of the GPIOs (comments) are probably wrong
- // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
+ // ICH10 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
@@ -124,7 +124,7 @@
}
- // ICH9 Root Complex Register Block. Memory Mapped through RCBA)
+ // ICH10 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve)
{
diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl
index 9d27b0b..1d9e54e 100644
--- a/src/southbridge/intel/i82801jx/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl
@@ -170,8 +170,8 @@
IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
- IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH9 ACPI
- IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH9 GPIO
+ IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH10 ACPI
+ IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH10 GPIO
})
}
diff --git a/src/southbridge/intel/i82801jx/acpi/pci.asl b/src/southbridge/intel/i82801jx/acpi/pci.asl
index f2988e1..de16424 100644
--- a/src/southbridge/intel/i82801jx/acpi/pci.asl
+++ b/src/southbridge/intel/i82801jx/acpi/pci.asl
@@ -65,7 +65,7 @@
Method (_PRT)
{
- #include "acpi/ich9_pci_irqs.asl"
+ #include "acpi/ich10_pci_irqs.asl"
}
}
diff --git a/src/southbridge/intel/i82801jx/acpi/usb.asl b/src/southbridge/intel/i82801jx/acpi/usb.asl
index 5fa751a..b621263 100644
--- a/src/southbridge/intel/i82801jx/acpi/usb.asl
+++ b/src/southbridge/intel/i82801jx/acpi/usb.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-/* Intel i82801I USB support */
+/* Intel i82801J USB support */
// USB Controller 0:1d.0
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c
index 6252712..cc685c4 100644
--- a/src/southbridge/intel/i82801jx/bootblock.c
+++ b/src/southbridge/intel/i82801jx/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include "i82801jx.h"
static void enable_spi_prefetch(void)
{
@@ -31,4 +32,8 @@
static void bootblock_southbridge_init(void)
{
enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
+ (uintptr_t)DEFAULT_RCBA | 1);
}
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index 307b751..f22748b 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -14,15 +14,15 @@
* GNU General Public License for more details.
*/
-#ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
-#define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
+#ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
+#define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
enum {
THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,
THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7
};
-struct southbridge_intel_i82801ix_config {
+struct southbridge_intel_i82801jx_config {
/**
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
@@ -88,4 +88,4 @@
uint8_t pcie_hotplug_map[8];
};
-#endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */
+#endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */
diff --git a/src/southbridge/intel/i82801jx/dmi_setup.c b/src/southbridge/intel/i82801jx/dmi_setup.c
index e47586b..83633a4 100644
--- a/src/southbridge/intel/i82801jx/dmi_setup.c
+++ b/src/southbridge/intel/i82801jx/dmi_setup.c
@@ -18,7 +18,7 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <northbridge/intel/gm45/gm45.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
/* VC1 Port Arbitration Table */
static const u8 vc1_pat[] = {
@@ -39,7 +39,7 @@
0x00, 0xf0, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
-void i82801ix_dmi_setup(void)
+void i82801jx_dmi_setup(void)
{
int i;
u32 reg32;
@@ -109,12 +109,12 @@
}
/* Should be called after VC1 has been enabled on both sides. */
-void i82801ix_dmi_poll_vc1(void)
+void i82801jx_dmi_poll_vc1(void)
{
int timeout;
timeout = 0x7ffff;
- printk(BIOS_DEBUG, "ICH9 waits for VC1 negotiation... ");
+ printk(BIOS_DEBUG, "ICH10 waits for VC1 negotiation... ");
while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {}
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
@@ -132,7 +132,7 @@
}
timeout = 0x7ffff;
- printk(BIOS_DEBUG, "ICH9 waits for port arbitration table update... ");
+ printk(BIOS_DEBUG, "ICH10 waits for port arbitration table update... ");
while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {}
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c
index c40f9b7..e2ac852 100644
--- a/src/southbridge/intel/i82801jx/early_init.c
+++ b/src/southbridge/intel/i82801jx/early_init.c
@@ -15,9 +15,9 @@
*/
#include <arch/io.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
-void i82801ix_early_init(void)
+void i82801jx_early_init(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index 31b33e9..fb6c252 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -19,7 +19,7 @@
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
#include "smbus.h"
void enable_smbus(void)
@@ -29,11 +29,6 @@
/* Set the SMBus device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x3);
- /* Check to make sure we've got the right device. */
- if (pci_read_config16(dev, 0x2) != 0x2930) {
- die("SMBus controller not found!");
- }
-
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c
index c3602c4..c75eee7 100644
--- a/src/southbridge/intel/i82801jx/hdaudio.c
+++ b/src/southbridge/intel/i82801jx/hdaudio.c
@@ -23,13 +23,13 @@
#include <arch/io.h>
#include <delay.h>
#include <device/azalia_device.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
#define HDA_ICII_REG 0x68
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-typedef struct southbridge_intel_i82801ix_config config_t;
+typedef struct southbridge_intel_i82801jx_config config_t;
static int set_bits(void *port, u32 mask, u32 val)
{
@@ -311,9 +311,14 @@
.ops_pci = &azalia_pci_ops,
};
-/* ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M */
-static const struct pci_driver i82801ix_azalia __pci_driver = {
+static const unsigned short pci_device_ids[] = {
+ 0x3a3e,
+ 0x3a6e,
+ 0
+};
+
+static const struct pci_driver i82801jx_azalia __pci_driver = {
.ops = &azalia_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x293e,
+ .devices = pci_device_ids,
};
diff --git a/src/southbridge/intel/i82801jx/i82801ix.c b/src/southbridge/intel/i82801jx/i82801jx.c
similarity index 86%
rename from src/southbridge/intel/i82801jx/i82801ix.c
rename to src/southbridge/intel/i82801jx/i82801jx.c
index 0f3a08c..dca3a41 100644
--- a/src/southbridge/intel/i82801jx/i82801ix.c
+++ b/src/southbridge/intel/i82801jx/i82801jx.c
@@ -21,11 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
-typedef struct southbridge_intel_i82801ix_config config_t;
+typedef struct southbridge_intel_i82801jx_config config_t;
-static void i82801ix_enable_device(device_t dev)
+static void i82801jx_enable_device(device_t dev)
{
u32 reg32;
@@ -35,7 +35,7 @@
pci_write_config32(dev, PCI_COMMAND, reg32);
}
-static void i82801ix_early_settings(const config_t *const info)
+static void i82801jx_early_settings(const config_t *const info)
{
/* Program FERR# as processor break event indicator. */
RCBA32(0x3410) |= (1 << 6);
@@ -49,7 +49,7 @@
RCBA32(0x352c) |= (3 << 16);
}
-static void i82801ix_pcie_init(const config_t *const info)
+static void i82801jx_pcie_init(const config_t *const info)
{
device_t pciePort[6];
int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */
@@ -113,7 +113,7 @@
}
}
-static void i82801ix_ehci_init(void)
+static void i82801jx_ehci_init(void)
{
const device_t pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));
if (!pciEHCI1)
@@ -134,7 +134,7 @@
(1 << 29) | (1 << 17) | (2 << 2));
}
-static int i82801ix_function_disabled(const unsigned devfn)
+static int i82801jx_function_disabled(const unsigned int devfn)
{
const struct device *const dev = dev_find_slot(0, devfn);
if (!dev) {
@@ -146,7 +146,7 @@
return !dev->enabled;
}
-static void i82801ix_hide_functions(void)
+static void i82801jx_hide_functions(void)
{
int i;
u32 reg32;
@@ -155,7 +155,7 @@
some functions have to be disabled in right order and/or have
other constraints. */
- if (i82801ix_function_disabled(PCI_DEVFN(0x19, 0)))
+ if (i82801jx_function_disabled(PCI_DEVFN(0x19, 0)))
RCBA32(RCBA_BUC) |= BUC_LAND;
reg32 = RCBA32(RCBA_FD);
@@ -185,7 +185,7 @@
{ PCI_DEVFN(0x1f, 6), FD_TTD }, /* Thermal Throttle */
};
for (i = 0; i < ARRAY_SIZE(functions); ++i) {
- if (i82801ix_function_disabled(functions[i].devfn))
+ if (i82801jx_function_disabled(functions[i].devfn))
reg32 |= functions[i].mask;
}
RCBA32(RCBA_FD) = reg32;
@@ -195,7 +195,7 @@
/* Hide PCIe root port PCI functions. RPFN is partially R/WO. */
reg32 = RCBA32(RCBA_RPFN);
for (i = 0; i < 6; ++i) {
- if (i82801ix_function_disabled(PCI_DEVFN(0x1c, i)))
+ if (i82801jx_function_disabled(PCI_DEVFN(0x1c, i)))
reg32 |= (1 << ((i * 4) + 3));
}
RCBA32(RCBA_RPFN) = reg32;
@@ -204,22 +204,22 @@
RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP);
}
-static void i82801ix_init(void *chip_info)
+static void i82801jx_init(void *chip_info)
{
const config_t *const info = (config_t *)chip_info;
- printk(BIOS_DEBUG, "Initializing i82801ix southbridge...\n");
+ printk(BIOS_DEBUG, "Initializing i82801jx southbridge...\n");
- i82801ix_early_settings(info);
+ i82801jx_early_settings(info);
/* PCI Express setup. */
- i82801ix_pcie_init(info);
+ i82801jx_pcie_init(info);
/* EHCI configuration. */
- i82801ix_ehci_init();
+ i82801jx_ehci_init();
/* Now hide internal functions. We can't access them after this. */
- i82801ix_hide_functions();
+ i82801jx_hide_functions();
/* Reset watchdog timer. */
#if !CONFIG_HAVE_SMI_HANDLER
@@ -228,8 +228,8 @@
outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */
}
-struct chip_operations southbridge_intel_i82801ix_ops = {
- CHIP_NAME("Intel ICH9/ICH9-M (82801Ix) Series Southbridge")
- .enable_dev = i82801ix_enable_device,
- .init = i82801ix_init,
+struct chip_operations southbridge_intel_i82801jx_ops = {
+ CHIP_NAME("Intel ICH10 (82801Jx) Series Southbridge")
+ .enable_dev = i82801jx_enable_device,
+ .init = i82801jx_init,
};
diff --git a/src/southbridge/intel/i82801jx/i82801ix.h b/src/southbridge/intel/i82801jx/i82801jx.h
similarity index 95%
rename from src/southbridge/intel/i82801jx/i82801ix.h
rename to src/southbridge/intel/i82801jx/i82801jx.h
index 6ec6d3f..1c765a3 100644
--- a/src/southbridge/intel/i82801jx/i82801ix.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -15,8 +15,8 @@
* GNU General Public License for more details.
*/
-#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H
-#define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H
+#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H
+#define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H
#ifndef __ACPI__
#ifndef __ASSEMBLER__
@@ -86,7 +86,9 @@
/* D31:F0 LPC bridge */
#define D31F0_PMBASE 0x40
+#define PMBASE D31F0_PMBASE
#define D31F0_ACPI_CNTL 0x44
+#define ACPI_CNTL D31F0_ACPI_CNTL
#define D31F0_GPIO_BASE 0x48
#define D31F0_GPIO_CNTL 0x4c
#define D31F0_PIRQA_ROUT 0x60
@@ -221,9 +223,9 @@
#if defined(__PRE_RAM__)
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
-void i82801ix_early_init(void);
-void i82801ix_dmi_setup(void);
-void i82801ix_dmi_poll_vc1(void);
+void i82801jx_early_init(void);
+void i82801jx_dmi_setup(void);
+void i82801jx_dmi_poll_vc1(void);
#endif
#endif
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 8212b0a..5d3b6b5 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -30,7 +30,7 @@
#include <arch/acpigen.h>
#include <cbmem.h>
#include <string.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
#include <drivers/intel/gma/i915.h>
@@ -40,9 +40,9 @@
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
-typedef struct southbridge_intel_i82801ix_config config_t;
+typedef struct southbridge_intel_i82801jx_config config_t;
-static void i82801ix_enable_apic(struct device *dev)
+static void i82801jx_enable_apic(struct device *dev)
{
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
@@ -62,7 +62,7 @@
setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
}
-static void i82801ix_enable_serial_irqs(struct device *dev)
+static void i82801jx_enable_serial_irqs(struct device *dev)
{
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, D31F0_SERIRQ_CNTL,
@@ -90,7 +90,7 @@
* 0x80 - The PIRQ is not routed.
*/
-static void i82801ix_pirq_init(device_t dev)
+static void i82801jx_pirq_init(device_t dev)
{
device_t irq_dev;
/* Get the chip configuration */
@@ -132,7 +132,7 @@
}
}
-static void i82801ix_gpi_routing(device_t dev)
+static void i82801jx_gpi_routing(device_t dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -161,7 +161,7 @@
pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
}
-static void i82801ix_power_options(device_t dev)
+static void i82801jx_power_options(device_t dev)
{
u8 reg8;
u16 reg16, pmbase;
@@ -245,7 +245,7 @@
// reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
#if DEBUG_PERIODIC_SMIS
- /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using
+ /* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using
* periodic SMIs.
*/
reg16 |= (3 << 0); // Periodic SMI every 8s
@@ -268,7 +268,7 @@
}
// Set the board's GPI routing.
- i82801ix_gpi_routing(dev);
+ i82801jx_gpi_routing(dev);
pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
@@ -293,7 +293,7 @@
outl(reg32, pmbase + 0x10);
}
-static void i82801ix_configure_cstates(device_t dev)
+static void i82801jx_configure_cstates(device_t dev)
{
u8 reg8;
@@ -311,7 +311,7 @@
/* We could enable slow-C4 exit here, if someone needs it? */
}
-static void i82801ix_rtc_init(struct device *dev)
+static void i82801jx_rtc_init(struct device *dev)
{
u8 reg8;
int rtc_failed;
@@ -370,7 +370,7 @@
}
#if CONFIG_HAVE_SMI_HANDLER
-static void i82801ix_lock_smm(struct device *dev)
+static void i82801jx_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
@@ -426,28 +426,28 @@
static void lpc_init(struct device *dev)
{
- printk(BIOS_DEBUG, "i82801ix: lpc_init\n");
+ printk(BIOS_DEBUG, "i82801jx: lpc_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
- i82801ix_enable_apic(dev);
+ i82801jx_enable_apic(dev);
- i82801ix_enable_serial_irqs(dev);
+ i82801jx_enable_serial_irqs(dev);
/* Setup the PIRQ. */
- i82801ix_pirq_init(dev);
+ i82801jx_pirq_init(dev);
/* Setup power options. */
- i82801ix_power_options(dev);
+ i82801jx_power_options(dev);
/* Configure Cx state registers */
if (LPC_IS_MOBILE(dev))
- i82801ix_configure_cstates(dev);
+ i82801jx_configure_cstates(dev);
/* Initialize the real time clock. */
- i82801ix_rtc_init(dev);
+ i82801jx_rtc_init(dev);
/* Initialize ISA DMA. */
isa_dma_init();
@@ -465,11 +465,11 @@
i8259_configure_irq_trigger(9, 1);
#if CONFIG_HAVE_SMI_HANDLER
- i82801ix_lock_smm(dev);
+ i82801jx_lock_smm(dev);
#endif
}
-static void i82801ix_lpc_read_resources(device_t dev)
+static void i82801jx_lpc_read_resources(device_t dev)
{
/*
* I/O Resources
@@ -571,7 +571,7 @@
};
static struct device_operations device_ops = {
- .read_resources = i82801ix_lpc_read_resources,
+ .read_resources = i82801jx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
@@ -583,16 +583,16 @@
};
static const unsigned short pci_device_ids[] = {
- 0x2912, /* ICH9DH */
- 0x2914, /* ICH9DO */
- 0x2916, /* ICH9R */
- 0x2918, /* ICH9 */
- 0x2917, /* ICH9M-E */
- 0x2919, /* ICH9M */
+ 0x3a10, /* ICH10R Eng. Sample */
+ 0x3a14, /* ICH10DO */
+ 0x3a16, /* ICH10R */
+ 0x3a18, /* ICH10 */
+ 0x3a1a, /* ICH10D */
+ 0x3a1e, /* ICH10 Eng. Sample */
0
};
-static const struct pci_driver ich9_lpc __pci_driver = {
+static const struct pci_driver ich10_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c
index 5da2e49..2262c91 100644
--- a/src/southbridge/intel/i82801jx/pci.c
+++ b/src/southbridge/intel/i82801jx/pci.c
@@ -17,7 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
static void pci_init(struct device *dev)
{
@@ -70,12 +70,11 @@
};
static const unsigned short pci_device_ids[] = {
- 0x244e, /* Desktop */
- 0x2448, /* Mobile */
+ 0x244e,
0
};
-static const struct pci_driver ich9_pci __pci_driver = {
+static const struct pci_driver ich10_pci __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index 502e765..01f65de 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -27,9 +27,9 @@
{
u16 reg16;
u32 reg32;
- struct southbridge_intel_i82801ix_config *config = dev->chip_info;
+ struct southbridge_intel_i82801jx_config *config = dev->chip_info;
- printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n");
+ printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n");
/* Enable Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -108,7 +108,7 @@
static void pch_pciexp_scan_bridge(device_t dev)
{
- struct southbridge_intel_i82801ix_config *config = dev->chip_info;
+ struct southbridge_intel_i82801jx_config *config = dev->chip_info;
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
@@ -131,17 +131,25 @@
.ops_pci = &pci_ops,
};
-/* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */
+/* 82801lJx, ICH10 */
static const unsigned short pci_device_ids[] = {
- 0x2940, /* Port 1 */
- 0x2942, /* Port 2 */
- 0x2944, /* Port 3 */
- 0x2946, /* Port 4 */
- 0x2948, /* Port 5 */
- 0x294a, /* Port 6 */
+ 0x3a40, /* Port 1 */
+ 0x3a42, /* Port 2 */
+ 0x3a44, /* Port 3 */
+ 0x3a46, /* Port 4 */
+ 0x3a48, /* Port 5 */
+ 0x3a4a, /* Port 6 */
+
+ 0x3a70, /* Port 1 */
+ 0x3a72, /* Port 2 */
+ 0x3a74, /* Port 3 */
+ 0x3a76, /* Port 4 */
+ 0x3a78, /* Port 5 */
+ 0x3a7a, /* Port 6 */
0
};
-static const struct pci_driver ich9_pcie __pci_driver = {
+
+static const struct pci_driver ich10_pcie __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c
index 8bfc476..9fe1f9e 100644
--- a/src/southbridge/intel/i82801jx/sata.c
+++ b/src/southbridge/intel/i82801jx/sata.c
@@ -20,10 +20,10 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
#include <pc80/mc146818rtc.h>
-typedef struct southbridge_intel_i82801ix_config config_t;
+typedef struct southbridge_intel_i82801jx_config config_t;
static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
const int is_mobile)
@@ -148,10 +148,10 @@
const int is_mobile = (devid == 0x2928) || (devid == 0x2929);
u8 sata_mode;
- printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n");
+ printk(BIOS_DEBUG, "i82801jx_sata: initializing...\n");
if (config == NULL) {
- printk(BIOS_ERR, "i82801ix_sata: error: "
+ printk(BIOS_ERR, "i82801jx_sata: error: "
"device not in devicetree.cb!\n");
return;
}
@@ -277,8 +277,14 @@
};
static const unsigned short pci_device_ids[] = {
- 0x2920, 0x2921, 0x2922, 0x2923,
- 0x2928, 0x2929,
+ 0x3a00,
+ 0x3a02,
+ 0x3a05,
+ 0x3a06,
+ 0x3a20,
+ 0x3a22,
+ 0x3a25,
+ 0x3a26,
0,
};
diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c
index 2113722..00894cf 100644
--- a/src/southbridge/intel/i82801jx/smbus.c
+++ b/src/southbridge/intel/i82801jx/smbus.c
@@ -103,7 +103,12 @@
.ops_pci = &smbus_pci_ops,
};
-static const unsigned short pci_device_ids[] = { 0x2930, 0 };
+static const unsigned short pci_device_ids[] =
+{
+ 0x3a30,
+ 0x3a60,
+ 0
+};
static const struct pci_driver pch_smbus __pci_driver = {
.ops = &smbus_ops,
diff --git a/src/southbridge/intel/i82801jx/smbus.h b/src/southbridge/intel/i82801jx/smbus.h
index bcc7587..61402f7 100644
--- a/src/southbridge/intel/i82801jx/smbus.h
+++ b/src/southbridge/intel/i82801jx/smbus.h
@@ -15,7 +15,7 @@
*/
#include <device/smbus_def.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
static void smbus_delay(void)
{
diff --git a/src/southbridge/intel/i82801jx/smi.c b/src/southbridge/intel/i82801jx/smi.c
index a6c28cb..06fa585 100644
--- a/src/southbridge/intel/i82801jx/smi.c
+++ b/src/southbridge/intel/i82801jx/smi.c
@@ -25,7 +25,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
/* I945/GM45 */
#define SMRAM 0x9d
@@ -276,7 +276,7 @@
smi_en |= TCO_EN;
smi_en |= APMC_EN;
#if DEBUG_PERIODIC_SMIS
- /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using
+ /* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using
* periodic SMIs.
*/
smi_en |= PERIODIC_EN;
diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c
index 7ad00ed..35e79c6 100644
--- a/src/southbridge/intel/i82801jx/smihandler.c
+++ b/src/southbridge/intel/i82801jx/smihandler.c
@@ -22,7 +22,7 @@
#include <cpu/x86/smm.h>
#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
#include "nvs.h"
diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c
index 12cf898..a5d5bed 100644
--- a/src/southbridge/intel/i82801jx/thermal.c
+++ b/src/southbridge/intel/i82801jx/thermal.c
@@ -20,7 +20,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
static void thermal_init(struct device *dev)
{
@@ -74,8 +74,14 @@
.ops_pci = &thermal_pci_ops,
};
-static const struct pci_driver ich9_thermal __pci_driver = {
+static const unsigned short pci_device_ids[] = {
+ 0x3a32,
+ 0x3a62,
+ 0
+};
+
+static const struct pci_driver ich10_thermal __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2932,
+ .devices = pci_device_ids,
};
diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c
index 7719f16..d5a0d97 100644
--- a/src/southbridge/intel/i82801jx/usb_ehci.c
+++ b/src/southbridge/intel/i82801jx/usb_ehci.c
@@ -18,7 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801ix.h"
+#include "i82801jx.h"
#include <device/pci_ehci.h>
static void usb_ehci_init(struct device *dev)
@@ -55,8 +55,10 @@
}
static const unsigned short pci_device_ids[] = {
- 0x293a,
- 0x293c,
+ 0x3a3a,
+ 0x3a6a,
+ 0x3a3c,
+ 0x3a6c,
0
};