commit 3473d16640081c984c102d489a3c927492051078
author Arthur Heymans <arthur@aheymans.xyz> Thu Mar 24 00:26:57 2022 +0100
committer Arthur Heymans <arthur@aheymans.xyz> Fri May 13 10:59:50 2022 +0000
tree 32fc225efcd4cac7d991f86d44160d26b39ed43a
parent 25a0c67e9d515f96bb8d3c3112715b03ac3944eb

drivers/intel/fsp1_1: Use C over CPP

This fixes building with clang.

Change-Id: Ida464d9ff96af3ff485682fbbf904bb2253ec44f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/drivers/intel/fsp1_1/fsp_util.c

diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 7dc16c3..1c205ae 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -89,26 +89,26 @@
 			(u8)((fsp_header->ImageRevision >> 16) & 0xff),
 			(u8)((fsp_header->ImageRevision >> 8) & 0xff),
 			(u8)(fsp_header->ImageRevision  & 0xff));
-#if CONFIG(DISPLAY_FSP_ENTRY_POINTS)
-	printk(BIOS_SPEW, "FSP Entry Points:\n");
-	printk(BIOS_SPEW, "    %p: Image Base\n", fsp_base);
-	printk(BIOS_SPEW, "    %p: TempRamInit\n",
-		&fsp_base[fsp_header->TempRamInitEntryOffset]);
-	printk(BIOS_SPEW, "    %p: FspInit\n",
-		&fsp_base[fsp_header->FspInitEntryOffset]);
-	if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
-		printk(BIOS_SPEW, "    %p: MemoryInit\n",
-			&fsp_base[fsp_header->FspMemoryInitEntryOffset]);
-		printk(BIOS_SPEW, "    %p: TempRamExit\n",
-			&fsp_base[fsp_header->TempRamExitEntryOffset]);
-		printk(BIOS_SPEW, "    %p: SiliconInit\n",
-			&fsp_base[fsp_header->FspSiliconInitEntryOffset]);
+	if (CONFIG(DISPLAY_FSP_ENTRY_POINTS)) {
+		printk(BIOS_SPEW, "FSP Entry Points:\n");
+		printk(BIOS_SPEW, "    %p: Image Base\n", fsp_base);
+		printk(BIOS_SPEW, "    %p: TempRamInit\n",
+		       &fsp_base[fsp_header->TempRamInitEntryOffset]);
+		printk(BIOS_SPEW, "    %p: FspInit\n",
+		       &fsp_base[fsp_header->FspInitEntryOffset]);
+		if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
+			printk(BIOS_SPEW, "    %p: MemoryInit\n",
+			       &fsp_base[fsp_header->FspMemoryInitEntryOffset]);
+			printk(BIOS_SPEW, "    %p: TempRamExit\n",
+			       &fsp_base[fsp_header->TempRamExitEntryOffset]);
+			printk(BIOS_SPEW, "    %p: SiliconInit\n",
+			       &fsp_base[fsp_header->FspSiliconInitEntryOffset]);
+		}
+		printk(BIOS_SPEW, "    %p: NotifyPhase\n",
+		       &fsp_base[fsp_header->NotifyPhaseEntryOffset]);
+		printk(BIOS_SPEW, "    %p: Image End\n",
+		       &fsp_base[fsp_header->ImageSize]);
 	}
-	printk(BIOS_SPEW, "    %p: NotifyPhase\n",
-		&fsp_base[fsp_header->NotifyPhaseEntryOffset]);
-	printk(BIOS_SPEW, "    %p: Image End\n",
-			&fsp_base[fsp_header->ImageSize]);
-#endif
 }
 
 void fsp_notify(u32 phase)