nb/intel/ironlake: Decouple `setup_heci_uma()` from northbridge
Remove all northbridge dependencies in the `setup_heci_uma()` function.
Update its signature to not pull in raminit internals and drop a dummy
read that doesn't have any side-effects (it's probably a leftover from
a replay of vendor firmware). This code will be moved into southbridge
scope in a follow-up.
Change-Id: Ie5b5c5f374e19512c5568ee8a292a82e146e67ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index c6d073e..55c10b7 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3598,7 +3598,12 @@
mchbar_write8(0x101c, 0xb8);
}
- setup_heci_uma(&info);
+ const u64 heci_uma_addr =
+ ((u64)
+ ((((u64)pci_read_config16(NORTHBRIDGE, TOM)) << 6) -
+ info.memory_reserved_for_heci_mb)) << 20;
+
+ setup_heci_uma(heci_uma_addr, info.memory_reserved_for_heci_mb);
if (info.uma_enabled) {
u16 ax;
diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h
index 05e5ac3..6dd07b3 100644
--- a/src/northbridge/intel/ironlake/raminit.h
+++ b/src/northbridge/intel/ironlake/raminit.h
@@ -106,6 +106,6 @@
void early_quickpath_init(struct raminfo *info, const u8 x2ca8);
void late_quickpath_init(struct raminfo *info, const int s3resume);
-void setup_heci_uma(struct raminfo *info);
+void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size);
#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/ironlake/raminit_heci.c b/src/northbridge/intel/ironlake/raminit_heci.c
index 5c636c9..e54b058 100644
--- a/src/northbridge/intel/ironlake/raminit_heci.c
+++ b/src/northbridge/intel/ironlake/raminit_heci.c
@@ -8,7 +8,6 @@
#include <southbridge/intel/ibexpeak/me.h>
#include <types.h>
-#define NORTHBRIDGE PCI_DEV(0, 0, 0)
#define HECIDEV PCI_DEV(0, 0x16, 0)
/* FIXME: add timeout. */
@@ -193,18 +192,12 @@
die("HECI init failed\n");
}
-void setup_heci_uma(struct raminfo *info)
+void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size)
{
- if (!info->memory_reserved_for_heci_mb && !(pci_read_config32(HECIDEV, 0x40) & 0x20))
+ if (!heci_uma_size && !(pci_read_config32(HECIDEV, 0x40) & 0x20))
return;
- const u64 heci_uma_addr =
- ((u64)
- ((((u64)pci_read_config16(NORTHBRIDGE, TOM)) << 6) -
- info->memory_reserved_for_heci_mb)) << 20;
-
- pci_read_config32(NORTHBRIDGE, DMIBAR);
- if (info->memory_reserved_for_heci_mb) {
+ if (heci_uma_size) {
dmibar_clrbits32(DMIVC0RCTL, 1 << 7);
RCBA32(0x14) &= ~0x80;
dmibar_clrbits32(DMIVC1RCTL, 1 << 7);
@@ -221,9 +214,9 @@
;
}
- mchbar_write32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
+ mchbar_write32(0x24, 0x10000 + heci_uma_size);
- send_heci_uma_message(heci_uma_addr, info->memory_reserved_for_heci_mb);
+ send_heci_uma_message(heci_uma_addr, heci_uma_size);
pci_write_config32(HECIDEV, 0x10, 0x0);
pci_write_config8(HECIDEV, 0x4, 0x0);