diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index c6a20fa..009db80 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -21,7 +21,7 @@
 #include <program_loading.h>
 #include "e7505.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	pci_devfn_t mch = PCI_DEV(0, 0, 0);
 	uintptr_t tolm;
diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c
index da9ed71..275ddd3 100644
--- a/src/northbridge/intel/fsp_rangeley/memmap.c
+++ b/src/northbridge/intel/fsp_rangeley/memmap.c
@@ -36,7 +36,7 @@
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
 }
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 7479a78..d34820e 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -117,7 +117,7 @@
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 007a67d..74d9292 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -34,7 +34,7 @@
 	return tom & ~((1 << 20) - 1);
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)smm_region_start();
 }
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 75a6c7e..d260af6 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -23,7 +23,7 @@
 #include <program_loading.h>
 #include "i440bx.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/* Base of TSEG is top of usable DRAM */
 	/*
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 8207d06..000ac7e 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -71,7 +71,7 @@
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1c17b0d..5de4b80 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -42,7 +42,7 @@
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index b4fef6b..0aa70cd 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -132,7 +132,7 @@
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 67de344..99888fa 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -31,7 +31,7 @@
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 41e4912..1924ddf 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -128,7 +128,7 @@
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;