soc/intel/xeon_sp: Remove NO_FSP_TEMP_RAM_EXIT from common config
For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not
be selected.
Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 1686479..0196e6d 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -11,6 +11,7 @@
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_0
+ select NO_FSP_TEMP_RAM_EXIT
help
Intel Skylake-SP support
@@ -19,6 +20,7 @@
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_2
select CACHE_MRC_SETTINGS
+ select NO_FSP_TEMP_RAM_EXIT
help
Intel Cooper Lake-SP support
@@ -38,7 +40,6 @@
select HAVE_SMI_HANDLER
select INTEL_CAR_NEM # For postcar only now
select INTEL_DESCRIPTOR_MODE_CAPABLE
- select NO_FSP_TEMP_RAM_EXIT
select PARALLEL_MP_AP_WORK
select PMC_GLOBAL_RESET_ENABLE_LOCK
select POSTCAR_STAGE