commit | 9a41333c6bb68a1ebb5cf9d2a0d21257124a735e | [log] [tgz] |
---|---|---|
author | EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> | Sat Nov 19 01:50:57 2022 +0800 |
committer | Felix Held <felix-coreboot@felixheld.de> | Wed Nov 23 14:00:06 2022 +0000 |
tree | 5a31902f8e5c8ab1cc9ecc210b0a7babc9081eb1 | |
parent | 6a22c5f8ee5b9883f0a99d786491d6d70eb167d7 [diff] |
mb/google/skyrim/var/winterhold: Add Vrm setting for SMT All parameters of DPTC_INPUT() need to be configured on devicetree when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without configurations on devicetree would be 0 when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document #57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA and vrm_soc_current_limit_mA on devicetree with thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoidany thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:258572474, b:248976976, b:259167917, b:257394883 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.