soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
This patch adds the following support to coreboot
1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B
partition of BIOS
2. Helper functions to support update.
Pre-requisites to enable IOM/NPHY FW Update:
1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and
FW_MAIN_B through board configuration files.
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path
SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path
2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition
NPHY/IOM update.
coreboot follows below procedure to update NPHY and IOM:
NPHY Update:
1. coreboot will navigate through the CSE region,
identify the CSE’s NPHY FW version and BIOS NPHY version.
2. Compare both versions, if there is a difference, CSE will trigger an
NPHY FW update. Otherwise, skips the NPHY FW update.
IOM Update:
1. coreboot will navigate through the CSE region, identify CSE's IOM
FW version and BIOS IOM version.
2. Compares both versions, if there is a difference, coreboot will
trigger an IOM FW update.Otherwise, skip IOM FW update.
Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT
PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE
boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only
if CSE boots from CSE RO Boot partition.
Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then
triggers update of NPHY and IOM FW in the CSE Region(RO and RW).
coreboot triggers NPHY/IOM update procedure in all ChromeOS boot
modes(Normal and Recovery).
BUG=b:202143532
BRANCH=None
TEST=Build and verify CSE sub-partitions IOM and NPHY are getting
updated with CBFS IOM and NPHY blobs.
Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after
the update.
Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/common/block/include/intelblocks/cse_layout.h b/src/soc/intel/common/block/include/intelblocks/cse_layout.h
new file mode 100644
index 0000000..4c88cc5
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/cse_layout.h
@@ -0,0 +1,105 @@
+/* BPDT version 1.7 support */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <sys/types.h>
+
+enum bpdt_entry_type {
+ SMIP = 0,
+ CSE_RBE = 1,
+ CSE_BUP = 2,
+ UCODE = 3,
+ IBB = 4,
+ S_BPDT = 5,
+ OBB = 6,
+ CSE_MAIN = 7,
+ ISH = 8,
+ CSE_IDLM = 9,
+ IFP_OVERRIDE = 10,
+ UTOK = 11,
+ UFS_PHY = 12,
+ UFS_GPP = 13,
+ PMC = 14,
+ IUNIT = 15,
+ NVM_CFG = 16,
+ UEP = 17,
+ OEM_KM = 20,
+ PAVP = 22,
+ IOM_FW = 23,
+ NPHY_FW = 24,
+ TBT_FW = 25,
+ ICC = 32,
+
+ MAX_SUBPARTS,
+};
+
+struct bpdt_header {
+ uint32_t signature; /* BPDT_SIGNATURE */
+ uint16_t descriptor_count;
+ uint8_t version; /* Layout 1.7 = 2 */
+ uint8_t flags;
+ uint32_t checksum;
+ uint32_t ifwi_version;
+ struct {
+ uint16_t major;
+ uint16_t minor;
+ uint16_t build;
+ uint16_t hotfix;
+ } fit_tool_version;
+} __packed;
+
+struct cse_layout {
+ uint8_t rom_bypass[16];
+ uint16_t size;
+ uint16_t redundancy;
+ uint32_t checksum;
+ uint32_t data_offset;
+ uint32_t data_size;
+ uint32_t bp1_offset;
+ uint32_t bp1_size;
+ uint32_t bp2_offset;
+ uint32_t bp2_size;
+ uint32_t bp3_offset;
+ uint32_t bp3_size;
+ uint32_t bp4_offset;
+ uint32_t bp4_size;
+ uint32_t bp5_offset;
+ uint32_t bp5_size;
+ uint32_t temp_base_addr;
+ uint32_t temp_base_size;
+ uint32_t flog_offset;
+ uint32_t flog_size;
+} __packed;
+
+struct bpdt_entry {
+ uint32_t type;
+ uint32_t offset;
+ uint32_t size;
+} __packed;
+
+struct subpart_hdr {
+ uint32_t signature; /* SUBPART_SIGNATURE */
+ uint32_t count;
+ uint8_t hdr_version; /* Header version = 2 */
+ uint8_t entry_version; /* Entry version = 1 */
+ uint8_t length;
+ uint8_t reserved;
+ uint8_t name[4];
+ uint32_t checksum;
+} __packed;
+
+struct subpart_entry {
+ uint8_t name[12];
+ uint32_t offset_bytes;
+ uint32_t length;
+ uint32_t rsvd2;
+} __packed;
+
+struct subpart_entry_manifest_header {
+ uint8_t reserved[36];
+ struct {
+ uint16_t major;
+ uint16_t minor;
+ uint16_t build;
+ uint16_t hotfix;
+ } binary_version;
+} __packed;