mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSD
Follow reference design rex0, toggles NVMe PWR pin as soon as
in early stage to make NVMe ready sooner.
BUG=none
TEST=Build karis and try warm reboot from OS console. Check the DUT
with WD SSD boots to OS again.
Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80213
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c
index 69921a8..8c0f929 100644
--- a/src/mainboard/google/rex/variants/karis/gpio.c
+++ b/src/mainboard/google/rex/variants/karis/gpio.c
@@ -367,6 +367,11 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+ /* GPP_A19 : [] ==> EN_PP3300_SSD */
+ PAD_CFG_GPO(GPP_A19, 0, DEEP),
+ /* GPP_A20 : [] ==> SSD_PERST_L */
+ PAD_CFG_GPO(GPP_A20, 1, DEEP),
+
/* GPP_B16 : [] ==> SOC_HDMI_HPD_L */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
/* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
@@ -393,9 +398,6 @@
/* GPP_E13 : [] ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
- /* GPP_A20 : [] ==> SSD_PERST_L */
- PAD_CFG_GPO(GPP_A20, 0, DEEP),
-
/* GPP_H10 : [] ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
@@ -404,6 +406,9 @@
};
static const struct pad_config romstage_gpio_table[] = {
+ /* GPP_A19 : [] ==> EN_PP3300_SSD */
+ PAD_CFG_GPO(GPP_A19, 1, DEEP),
+
/* GPP_B11 : [] ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_B11, 0, DEEP),
/* A20 : [] ==> SSD_PERST_L */