commit 32e1022611d232af0d1b817bc5d8adeb7cf8f6a2
author Subrata Banik <subratabanik@google.com> Wed Apr 13 12:06:39 2022 +0530
committer Felix Held <felix-coreboot@felixheld.de> Thu Apr 14 15:41:45 2022 +0000
tree 0b7c11c82e6a2f2907d62935debf05d0fe8faa7a
parent e7089e12a13e96e61216d94db85a1c6a1347449d

soc/intel/cmn/{block, pch}: Rename configs from `DMI` to `GPMR`

This patch renames all required IA common code blocks and PCH configs
from DMI to GPMR.

TEST=Able to build and boot google/redrix.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic6e576dd7f207eb16d90c5cc2892d919980d91c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

src/soc/intel/common/block/lpc/lpc_lib.c

diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 1393714..2bd9858 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -24,7 +24,7 @@
 	reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
 	io_enables |= reg_io_enables;
 	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
 		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
 
 	return io_enables;
@@ -42,7 +42,7 @@
 	reg_io_ranges = lpc_get_fixed_io_decode() & ~mask;
 	io_ranges |= reg_io_ranges & mask;
 	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges);
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
 		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges);
 
 	return io_ranges;
@@ -112,7 +112,7 @@
 		lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
 
 		pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
-		if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+		if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
 			pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir);
 
 		printk(BIOS_DEBUG,
@@ -147,7 +147,7 @@
 	lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN;
 
 	pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
 		pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr);
 }
 
@@ -248,7 +248,7 @@
 	/* Set in PCI generic decode range registers */
 	for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
 		pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]);
-		if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+		if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
 			pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]);
 	}
 }