soc/intel/cmn/{block, pch}: Rename configs from `DMI` to `GPMR`
This patch renames all required IA common code blocks and PCH configs
from DMI to GPMR.
TEST=Able to build and boot google/redrix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic6e576dd7f207eb16d90c5cc2892d919980d91c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/common/block/gpmr/Kconfig b/src/soc/intel/common/block/gpmr/Kconfig
index 2cc4646..8ca26b4 100644
--- a/src/soc/intel/common/block/gpmr/Kconfig
+++ b/src/soc/intel/common/block/gpmr/Kconfig
@@ -1,5 +1,5 @@
-config SOC_INTEL_COMMON_BLOCK_DMI
+config SOC_INTEL_COMMON_BLOCK_GPMR
bool
select SOC_INTEL_COMMON_BLOCK_PCR
help
- Intel Processor common DMI support
+ Intel Processor common GPMR support
diff --git a/src/soc/intel/common/block/gpmr/Makefile.inc b/src/soc/intel/common/block/gpmr/Makefile.inc
index 0abf61f..2725fe1 100644
--- a/src/soc/intel/common/block/gpmr/Makefile.inc
+++ b/src/soc/intel/common/block/gpmr/Makefile.inc
@@ -1,4 +1,4 @@
-ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y)
+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR), y)
bootblock-y += gpmr.c
romstage-y += gpmr.c
diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig
index d76620a..2fac5ff 100644
--- a/src/soc/intel/common/block/lpc/Kconfig
+++ b/src/soc/intel/common/block/lpc/Kconfig
@@ -12,9 +12,9 @@
By default COMA range to LPC is enable. COMB range to LPC is optional
and should select based on platform dedicated selection.
-config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
+config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR
bool
- depends on SOC_INTEL_COMMON_BLOCK_DMI
+ depends on SOC_INTEL_COMMON_BLOCK_GPMR
help
- Mirror LPC registers for IO/MMIO to their corresponding DMI registers.
+ Mirror LPC registers for IO/MMIO to their corresponding GPMR registers.
Required for platforms starting from SPT.
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 1393714..2bd9858 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -24,7 +24,7 @@
reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
io_enables |= reg_io_enables;
pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
return io_enables;
@@ -42,7 +42,7 @@
reg_io_ranges = lpc_get_fixed_io_decode() & ~mask;
io_ranges |= reg_io_ranges & mask;
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges);
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges);
return io_ranges;
@@ -112,7 +112,7 @@
lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir);
printk(BIOS_DEBUG,
@@ -147,7 +147,7 @@
lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN;
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr);
}
@@ -248,7 +248,7 @@
/* Set in PCI generic decode range registers */
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]);
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]);
}
}
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index 1ad72d8..56471c3 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -26,13 +26,13 @@
def_bool y
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CSE
- select SOC_INTEL_COMMON_BLOCK_DMI
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
+ select SOC_INTEL_COMMON_BLOCK_GPMR
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_LPC
- select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
+ select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR
select SOC_INTEL_COMMON_BLOCK_P2SB
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_PMC