| commit | 32ca3ac9abba771213a180699e07132e8558ce37 | [log] [tgz] |
|---|---|---|
| author | Felix Singer <felixsinger@posteo.net> | Sat Jul 17 04:58:16 2021 +0200 |
| committer | Nico Huber <nico.h@gmx.de> | Mon Jul 26 12:21:26 2021 +0000 |
| tree | 169a539e8b421cf424400cacb1ed88b2c254d9e8 | |
| parent | ca3aa52cf8be153523c931646e850f8f2b433fc0 [diff] |
mb/intel/coffeelake_rvp: Use CHIPSET_LOCKDOWN_COREBOOT Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown on all variants. Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 12b1c47..49c400f 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
@@ -1,5 +1,7 @@ chip soc/intel/cannonlake + register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + device cpu_cluster 0 on device lapic 0 on end end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index f4b82ab..f20622c9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -48,11 +48,9 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C3 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[3] = { .speed = I2C_SPEED_STANDARD, .rise_time_ns = 104,