cpu: Add CPU microcode file to cbfs with 16-byte alignment

On x86 there is a 16-byte alignment requirement for the
addresses containing the CPU microcode. The cbfs files
containing the microcode are used in memory-mapped fashion
when loading new mircocode. Therefore, the data payload's
address/offset of a cbfs file in flash dictates the resulting
alignment. Fix this by processing the CPU microcode cbfs
file separately as it uses $(CBFSTOOL) to find the proper
location within the provided rom image.

Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index 1ef78d1..27a0df6 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -46,7 +46,7 @@
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
 # TODO Change -b to Kconfig variable.
-$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL)
+$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
 	$(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
 		-B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \
 		-H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \
@@ -56,6 +56,7 @@
 		-f $(objcbfs)/romstage.elf -b 0 \
 		-n $(CONFIG_CBFS_PREFIX)/romstage -c none
 	$(prebuild-files) true
+	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 .PHONY: $(obj)/coreboot.pre
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7f1b7b2..0faf140 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -61,11 +61,12 @@
 	$(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&)
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
-$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL)
+$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
 	$(CBFSTOOL) $@.tmp create -m x86 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
 		-B $(objcbfs)/bootblock.bin -a 64 \
 		-o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
 	$(prebuild-files) true
+	$(call add-cpu-microcode-to-cbfs,$@.tmp)
 	mv $@.tmp $@
 else
 .PHONY: $(obj)/coreboot.pre1
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 09d36ec..a860f67 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -15,17 +15,17 @@
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
+cpu_ucode_cbfs_name = cpu_microcode_blob.bin
+
 # External microcode file, or are we generating one ?
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
-cbfs-files-y += cpu_microcode_blob.bin
-cpu_microcode_blob.bin-type = 0x53
-cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
+cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
+cbfs_include_ucode = y
 endif
 
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y)
-cbfs-files-y += cpu_microcode_blob.bin
-cpu_microcode_blob.bin-type = 0x53
-cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin
+cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
+cbfs_include_ucode = y
 endif
 
 # In case we have more than one "source" (cough) files containing microcode, we
@@ -42,3 +42,11 @@
 $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
 	@printf "  MICROCODE    $(subst $(obj)/,,$(@))\n"
 	$(OBJCOPY) -j .data -O binary $< $@
+
+ifeq ($(cbfs_include_ucode),y)
+# Add CPU microcode to specified rom image $(1)
+add-cpu-microcode-to-cbfs = \
+	$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 -b
+else
+add-cpu-microcode-to-cbfs = true
+endif