tree e7ce5af5e3ba36f72ec2acc59948d28d97c9d358
parent 333652c5b2dd3291a73f922e0b86c3ab9612f4b1
author Ben Chuang <benchuanggli@gmail.com> 1631590302 +0800
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1632506169 +0000

drivers/genesyslogic/gl9755: Disable ASPM L0s support

When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.

BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>